STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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stm32f4xx_hal_dma.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef __STM32F4xx_HAL_DMA_H
21#define __STM32F4xx_HAL_DMA_H
22
23#ifdef __cplusplus
24 extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f4xx_hal_def.h"
29
38/* Exported types ------------------------------------------------------------*/
39
48typedef struct
49{
50 uint32_t Channel;
53 uint32_t Direction;
57 uint32_t PeriphInc;
60 uint32_t MemInc;
63 uint32_t PeriphDataAlignment;
66 uint32_t MemDataAlignment;
69 uint32_t Mode;
74 uint32_t Priority;
77 uint32_t FIFOMode;
82 uint32_t FIFOThreshold;
85 uint32_t MemBurst;
91 uint32_t PeriphBurst;
96}DMA_InitTypeDef;
97
98
111
120
134
169
174/* Exported constants --------------------------------------------------------*/
175
185#define HAL_DMA_ERROR_NONE 0x00000000U
186#define HAL_DMA_ERROR_TE 0x00000001U
187#define HAL_DMA_ERROR_FE 0x00000002U
188#define HAL_DMA_ERROR_DME 0x00000004U
189#define HAL_DMA_ERROR_TIMEOUT 0x00000020U
190#define HAL_DMA_ERROR_PARAM 0x00000040U
191#define HAL_DMA_ERROR_NO_XFER 0x00000080U
192#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
201#define DMA_CHANNEL_0 0x00000000U
202#define DMA_CHANNEL_1 0x02000000U
203#define DMA_CHANNEL_2 0x04000000U
204#define DMA_CHANNEL_3 0x06000000U
205#define DMA_CHANNEL_4 0x08000000U
206#define DMA_CHANNEL_5 0x0A000000U
207#define DMA_CHANNEL_6 0x0C000000U
208#define DMA_CHANNEL_7 0x0E000000U
209#if defined (DMA_SxCR_CHSEL_3)
210#define DMA_CHANNEL_8 0x10000000U
211#define DMA_CHANNEL_9 0x12000000U
212#define DMA_CHANNEL_10 0x14000000U
213#define DMA_CHANNEL_11 0x16000000U
214#define DMA_CHANNEL_12 0x18000000U
215#define DMA_CHANNEL_13 0x1A000000U
216#define DMA_CHANNEL_14 0x1C000000U
217#define DMA_CHANNEL_15 0x1E000000U
218#endif /* DMA_SxCR_CHSEL_3 */
227#define DMA_PERIPH_TO_MEMORY 0x00000000U
228#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
229#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)
238#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
239#define DMA_PINC_DISABLE 0x00000000U
248#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
249#define DMA_MINC_DISABLE 0x00000000U
258#define DMA_PDATAALIGN_BYTE 0x00000000U
259#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
260#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)
269#define DMA_MDATAALIGN_BYTE 0x00000000U
270#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
271#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)
280#define DMA_NORMAL 0x00000000U
281#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
282#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
291#define DMA_PRIORITY_LOW 0x00000000U
292#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
293#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
294#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)
303#define DMA_FIFOMODE_DISABLE 0x00000000U
304#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)
313#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U
314#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
315#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
316#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)
325#define DMA_MBURST_SINGLE 0x00000000U
326#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
327#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
328#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
337#define DMA_PBURST_SINGLE 0x00000000U
338#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
339#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
340#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
349#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
350#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
351#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
352#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
353#define DMA_IT_FE 0x00000080U
362#define DMA_FLAG_FEIF0_4 0x00000001U
363#define DMA_FLAG_DMEIF0_4 0x00000004U
364#define DMA_FLAG_TEIF0_4 0x00000008U
365#define DMA_FLAG_HTIF0_4 0x00000010U
366#define DMA_FLAG_TCIF0_4 0x00000020U
367#define DMA_FLAG_FEIF1_5 0x00000040U
368#define DMA_FLAG_DMEIF1_5 0x00000100U
369#define DMA_FLAG_TEIF1_5 0x00000200U
370#define DMA_FLAG_HTIF1_5 0x00000400U
371#define DMA_FLAG_TCIF1_5 0x00000800U
372#define DMA_FLAG_FEIF2_6 0x00010000U
373#define DMA_FLAG_DMEIF2_6 0x00040000U
374#define DMA_FLAG_TEIF2_6 0x00080000U
375#define DMA_FLAG_HTIF2_6 0x00100000U
376#define DMA_FLAG_TCIF2_6 0x00200000U
377#define DMA_FLAG_FEIF3_7 0x00400000U
378#define DMA_FLAG_DMEIF3_7 0x01000000U
379#define DMA_FLAG_TEIF3_7 0x02000000U
380#define DMA_FLAG_HTIF3_7 0x04000000U
381#define DMA_FLAG_TCIF3_7 0x08000000U
390/* Exported macro ------------------------------------------------------------*/
391
396#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
397
410#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
411
417#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
418
424#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
425
426/* Interrupt & Flag management */
427
433#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
434(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
435 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
436 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
438 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
439 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
440 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
441 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
442 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
446 DMA_FLAG_TCIF3_7)
447
453#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
454(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
466 DMA_FLAG_HTIF3_7)
467
473#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
474(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
486 DMA_FLAG_TEIF3_7)
487
493#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
494(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
506 DMA_FLAG_FEIF3_7)
507
513#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
514(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
526 DMA_FLAG_DMEIF3_7)
527
541#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
542(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
543 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
544 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
545
559#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
560(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
561 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
562 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
563
576#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
577((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
578
591#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
592((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
593
606#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
607 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
608 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
609
627#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
628
635#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
636
637
638/* Include DMA HAL Extension module */
639#include "stm32f4xx_hal_dma_ex.h"
640
641/* Exported functions --------------------------------------------------------*/
642
652HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
653HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
662HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
663HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
664HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
665HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
666HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
667void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
668HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
669HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
670HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
671
680HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
681uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
688/* Private Constants -------------------------------------------------------------*/
697/* Private macros ------------------------------------------------------------*/
702#if defined (DMA_SxCR_CHSEL_3)
703#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
704 ((CHANNEL) == DMA_CHANNEL_1) || \
705 ((CHANNEL) == DMA_CHANNEL_2) || \
706 ((CHANNEL) == DMA_CHANNEL_3) || \
707 ((CHANNEL) == DMA_CHANNEL_4) || \
708 ((CHANNEL) == DMA_CHANNEL_5) || \
709 ((CHANNEL) == DMA_CHANNEL_6) || \
710 ((CHANNEL) == DMA_CHANNEL_7) || \
711 ((CHANNEL) == DMA_CHANNEL_8) || \
712 ((CHANNEL) == DMA_CHANNEL_9) || \
713 ((CHANNEL) == DMA_CHANNEL_10)|| \
714 ((CHANNEL) == DMA_CHANNEL_11)|| \
715 ((CHANNEL) == DMA_CHANNEL_12)|| \
716 ((CHANNEL) == DMA_CHANNEL_13)|| \
717 ((CHANNEL) == DMA_CHANNEL_14)|| \
718 ((CHANNEL) == DMA_CHANNEL_15))
719#else
720#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
721 ((CHANNEL) == DMA_CHANNEL_1) || \
722 ((CHANNEL) == DMA_CHANNEL_2) || \
723 ((CHANNEL) == DMA_CHANNEL_3) || \
724 ((CHANNEL) == DMA_CHANNEL_4) || \
725 ((CHANNEL) == DMA_CHANNEL_5) || \
726 ((CHANNEL) == DMA_CHANNEL_6) || \
727 ((CHANNEL) == DMA_CHANNEL_7))
728#endif /* DMA_SxCR_CHSEL_3 */
729
730#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
731 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
732 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
733
734#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
735
736#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
737 ((STATE) == DMA_PINC_DISABLE))
738
739#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
740 ((STATE) == DMA_MINC_DISABLE))
741
742#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
743 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
744 ((SIZE) == DMA_PDATAALIGN_WORD))
745
746#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
747 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
748 ((SIZE) == DMA_MDATAALIGN_WORD ))
749
750#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
751 ((MODE) == DMA_CIRCULAR) || \
752 ((MODE) == DMA_PFCTRL))
753
754#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
755 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
756 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
757 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
758
759#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
760 ((STATE) == DMA_FIFOMODE_ENABLE))
761
762#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
763 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
764 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
765 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
766
767#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
768 ((BURST) == DMA_MBURST_INC4) || \
769 ((BURST) == DMA_MBURST_INC8) || \
770 ((BURST) == DMA_MBURST_INC16))
771
772#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
773 ((BURST) == DMA_PBURST_INC4) || \
774 ((BURST) == DMA_PBURST_INC8) || \
775 ((BURST) == DMA_PBURST_INC16))
780/* Private functions ---------------------------------------------------------*/
797#ifdef __cplusplus
798}
799#endif
800
801#endif /* __STM32F4xx_HAL_DMA_H */
802
HAL_DMA_Init
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and create the associ...
Definition stm32f4xx_hal_dma.c:170
HAL_DMA_DeInit
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
DeInitializes the DMA peripheral.
Definition stm32f4xx_hal_dma.c:309
HAL_DMA_Abort
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
Definition stm32f4xx_hal_dma.c:513
HAL_DMA_Abort_IT
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
Definition stm32f4xx_hal_dma.c:580
HAL_DMA_Start_IT
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
Definition stm32f4xx_hal_dma.c:451
HAL_DMA_UnRegisterCallback
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
Definition stm32f4xx_hal_dma.c:1029
HAL_DMA_IRQHandler
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
Definition stm32f4xx_hal_dma.c:746
HAL_DMA_Start
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Starts the DMA Transfer.
Definition stm32f4xx_hal_dma.c:407
HAL_DMA_PollForTransfer
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
Definition stm32f4xx_hal_dma.c:610
HAL_DMA_RegisterCallback
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
Definition stm32f4xx_hal_dma.c:967
HAL_DMA_CleanCallbacks
HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma)
HAL_DMA_GetError
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
Return the DMA error code.
Definition stm32f4xx_hal_dma.c:1125
HAL_DMA_GetState
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
Returns the DMA state.
Definition stm32f4xx_hal_dma.c:1114
DMA_HandleTypeDef
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
HAL_DMA_StateTypeDef
HAL_DMA_StateTypeDef
HAL DMA State structures definition.
Definition stm32f4xx_hal_dma.h:103
HAL_DMA_LevelCompleteTypeDef
HAL_DMA_LevelCompleteTypeDef
HAL DMA Error Code structure definition.
Definition stm32f4xx_hal_dma.h:116
HAL_DMA_CallbackIDTypeDef
HAL_DMA_CallbackIDTypeDef
HAL DMA Error Code structure definition.
Definition stm32f4xx_hal_dma.h:125
HAL_DMA_STATE_RESET
@ HAL_DMA_STATE_RESET
Definition stm32f4xx_hal_dma.h:104
HAL_DMA_STATE_ERROR
@ HAL_DMA_STATE_ERROR
Definition stm32f4xx_hal_dma.h:108
HAL_DMA_STATE_TIMEOUT
@ HAL_DMA_STATE_TIMEOUT
Definition stm32f4xx_hal_dma.h:107
HAL_DMA_STATE_READY
@ HAL_DMA_STATE_READY
Definition stm32f4xx_hal_dma.h:105
HAL_DMA_STATE_ABORT
@ HAL_DMA_STATE_ABORT
Definition stm32f4xx_hal_dma.h:109
HAL_DMA_STATE_BUSY
@ HAL_DMA_STATE_BUSY
Definition stm32f4xx_hal_dma.h:106
HAL_DMA_FULL_TRANSFER
@ HAL_DMA_FULL_TRANSFER
Definition stm32f4xx_hal_dma.h:117
HAL_DMA_HALF_TRANSFER
@ HAL_DMA_HALF_TRANSFER
Definition stm32f4xx_hal_dma.h:118
HAL_DMA_XFER_M1CPLT_CB_ID
@ HAL_DMA_XFER_M1CPLT_CB_ID
Definition stm32f4xx_hal_dma.h:128
HAL_DMA_XFER_ABORT_CB_ID
@ HAL_DMA_XFER_ABORT_CB_ID
Definition stm32f4xx_hal_dma.h:131
HAL_DMA_XFER_ERROR_CB_ID
@ HAL_DMA_XFER_ERROR_CB_ID
Definition stm32f4xx_hal_dma.h:130
HAL_DMA_XFER_HALFCPLT_CB_ID
@ HAL_DMA_XFER_HALFCPLT_CB_ID
Definition stm32f4xx_hal_dma.h:127
HAL_DMA_XFER_CPLT_CB_ID
@ HAL_DMA_XFER_CPLT_CB_ID
Definition stm32f4xx_hal_dma.h:126
HAL_DMA_XFER_M1HALFCPLT_CB_ID
@ HAL_DMA_XFER_M1HALFCPLT_CB_ID
Definition stm32f4xx_hal_dma.h:129
HAL_DMA_XFER_ALL_CB_ID
@ HAL_DMA_XFER_ALL_CB_ID
Definition stm32f4xx_hal_dma.h:132
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition stm32f4xx_hal_def.h:39
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition stm32f4xx_hal_def.h:50
stm32f4xx_hal_dma_ex.h
Header file of DMA HAL extension module.
DMA_InitTypeDef
DMA Configuration Structure definition.
Definition stm32f4xx_hal_dma.h:49
DMA_InitTypeDef::Direction
uint32_t Direction
Definition stm32f4xx_hal_dma.h:53
DMA_InitTypeDef::PeriphDataAlignment
uint32_t PeriphDataAlignment
Definition stm32f4xx_hal_dma.h:63
DMA_InitTypeDef::FIFOThreshold
uint32_t FIFOThreshold
Definition stm32f4xx_hal_dma.h:82
DMA_InitTypeDef::PeriphBurst
uint32_t PeriphBurst
Definition stm32f4xx_hal_dma.h:91
DMA_InitTypeDef::PeriphInc
uint32_t PeriphInc
Definition stm32f4xx_hal_dma.h:57
DMA_InitTypeDef::MemInc
uint32_t MemInc
Definition stm32f4xx_hal_dma.h:60
DMA_InitTypeDef::MemDataAlignment
uint32_t MemDataAlignment
Definition stm32f4xx_hal_dma.h:66
DMA_InitTypeDef::FIFOMode
uint32_t FIFOMode
Definition stm32f4xx_hal_dma.h:77
DMA_InitTypeDef::MemBurst
uint32_t MemBurst
Definition stm32f4xx_hal_dma.h:85
DMA_InitTypeDef::Mode
uint32_t Mode
Definition stm32f4xx_hal_dma.h:69
DMA_InitTypeDef::Priority
uint32_t Priority
Definition stm32f4xx_hal_dma.h:74
DMA_InitTypeDef::Channel
uint32_t Channel
Definition stm32f4xx_hal_dma.h:50
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition stm32f4xx_hal_dma.h:139
__DMA_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition stm32f4xx_hal_dma.h:144
__DMA_HandleTypeDef::XferAbortCallback
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
Definition stm32f4xx_hal_dma.h:160
__DMA_HandleTypeDef::Init
DMA_InitTypeDef Init
Definition stm32f4xx_hal_dma.h:142
__DMA_HandleTypeDef::StreamIndex
uint32_t StreamIndex
Definition stm32f4xx_hal_dma.h:166
__DMA_HandleTypeDef::XferCpltCallback
void(* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition stm32f4xx_hal_dma.h:150
__DMA_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition stm32f4xx_hal_dma.h:162
__DMA_HandleTypeDef::XferErrorCallback
void(* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)
Definition stm32f4xx_hal_dma.h:158
__DMA_HandleTypeDef::State
__IO HAL_DMA_StateTypeDef State
Definition stm32f4xx_hal_dma.h:146
__DMA_HandleTypeDef::XferHalfCpltCallback
void(* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition stm32f4xx_hal_dma.h:152
__DMA_HandleTypeDef::StreamBaseAddress
uint32_t StreamBaseAddress
Definition stm32f4xx_hal_dma.h:164
__DMA_HandleTypeDef::Instance
DMA_Stream_TypeDef * Instance
Definition stm32f4xx_hal_dma.h:140
__DMA_HandleTypeDef::XferM1HalfCpltCallback
void(* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition stm32f4xx_hal_dma.h:156
__DMA_HandleTypeDef::XferM1CpltCallback
void(* XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition stm32f4xx_hal_dma.h:154
__DMA_HandleTypeDef::Parent
void * Parent
Definition stm32f4xx_hal_dma.h:148