STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
Loading...
Searching...
No Matches
stm32f4xx_hal_nand.h
Go to the documentation of this file.
1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32F4xx_HAL_NAND_H
21#define STM32F4xx_HAL_NAND_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3)
28
29/* Includes ------------------------------------------------------------------*/
30#if defined(FSMC_Bank2_3)
31#include "stm32f4xx_ll_fsmc.h"
32#else
33#include "stm32f4xx_ll_fmc.h"
34#endif /* FSMC_Bank2_3 */
35
44/* Exported typedef ----------------------------------------------------------*/
45/* Exported types ------------------------------------------------------------*/
53typedef enum
54{
55 HAL_NAND_STATE_RESET = 0x00U,
56 HAL_NAND_STATE_READY = 0x01U,
57 HAL_NAND_STATE_BUSY = 0x02U,
58 HAL_NAND_STATE_ERROR = 0x03U
59} HAL_NAND_StateTypeDef;
60
64typedef struct
65{
66 /*<! NAND memory electronic signature maker and device IDs */
67
68 uint8_t Maker_Id;
69
70 uint8_t Device_Id;
71
72 uint8_t Third_Id;
73
74 uint8_t Fourth_Id;
75} NAND_IDTypeDef;
76
80typedef struct
81{
82 uint16_t Page;
84 uint16_t Plane;
86 uint16_t Block;
88} NAND_AddressTypeDef;
89
93typedef struct
94{
95 uint32_t PageSize;
98 uint32_t SpareAreaSize;
101 uint32_t BlockSize;
103 uint32_t BlockNbr;
105 uint32_t PlaneNbr;
107 uint32_t PlaneSize;
109 FunctionalState ExtraCommandEnable;
114} NAND_DeviceConfigTypeDef;
115
119#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
120typedef struct __NAND_HandleTypeDef
121#else
122typedef struct
123#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
124{
125 FMC_NAND_TypeDef *Instance;
127 FMC_NAND_InitTypeDef Init;
129 HAL_LockTypeDef Lock;
131 __IO HAL_NAND_StateTypeDef State;
133 NAND_DeviceConfigTypeDef Config;
135#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
136 void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand);
137 void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand);
138 void (* ItCallback)(struct __NAND_HandleTypeDef *hnand);
139#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
140} NAND_HandleTypeDef;
141
142#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
146typedef enum
147{
148 HAL_NAND_MSP_INIT_CB_ID = 0x00U,
149 HAL_NAND_MSP_DEINIT_CB_ID = 0x01U,
150 HAL_NAND_IT_CB_ID = 0x02U
151} HAL_NAND_CallbackIDTypeDef;
152
156typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
157#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
158
163/* Exported constants --------------------------------------------------------*/
164/* Exported macro ------------------------------------------------------------*/
173#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
174#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \
175 (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
176 (__HANDLE__)->MspInitCallback = NULL; \
177 (__HANDLE__)->MspDeInitCallback = NULL; \
178 } while(0)
179#else
180#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
181#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
182
187/* Exported functions --------------------------------------------------------*/
196/* Initialization/de-initialization functions ********************************/
197HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
198 FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
199HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
200
201HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
202
203HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
204
205void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
206void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
207void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
208void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
209
218/* IO operation functions ****************************************************/
219HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
220
221HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
222 uint8_t *pBuffer, uint32_t NumPageToRead);
223HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
224 const uint8_t *pBuffer, uint32_t NumPageToWrite);
225HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
226 uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
227HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
228 const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
229
230HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
231 uint16_t *pBuffer, uint32_t NumPageToRead);
232HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
233 const uint16_t *pBuffer, uint32_t NumPageToWrite);
234HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
235 uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
236HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
237 const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
238
239HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
240
241uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
242
243#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
244/* NAND callback registering/unregistering */
245HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
246 pNAND_CallbackTypeDef pCallback);
247HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
248#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
249
258/* NAND Control functions ****************************************************/
259HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
260HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
261HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
262
270/* NAND State functions *******************************************************/
271HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
272uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
281/* Private types -------------------------------------------------------------*/
282/* Private variables ---------------------------------------------------------*/
283/* Private constants ---------------------------------------------------------*/
287#if defined(FMC_Bank2_3)
288#define NAND_DEVICE1 0x70000000UL
289#define NAND_DEVICE2 0x80000000UL
290#else
291#define NAND_DEVICE 0x80000000UL
292#endif /* NAND_SECOND_BANK */
293#define NAND_WRITE_TIMEOUT 0x01000000UL
294
295#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
296#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
297
298#define NAND_CMD_AREA_A ((uint8_t)0x00)
299#define NAND_CMD_AREA_B ((uint8_t)0x01)
300#define NAND_CMD_AREA_C ((uint8_t)0x50)
301#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
302
303#define NAND_CMD_WRITE0 ((uint8_t)0x80)
304#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
305#define NAND_CMD_ERASE0 ((uint8_t)0x60)
306#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
307#define NAND_CMD_READID ((uint8_t)0x90)
308#define NAND_CMD_STATUS ((uint8_t)0x70)
309#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
310#define NAND_CMD_RESET ((uint8_t)0xFF)
311
312/* NAND memory status */
313#define NAND_VALID_ADDRESS 0x00000100UL
314#define NAND_INVALID_ADDRESS 0x00000200UL
315#define NAND_TIMEOUT_ERROR 0x00000400UL
316#define NAND_BUSY 0x00000000UL
317#define NAND_ERROR 0x00000001UL
318#define NAND_READY 0x00000040UL
323/* Private macros ------------------------------------------------------------*/
334#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
335 (((__ADDRESS__)->Block + \
336 (((__ADDRESS__)->Plane) * \
337 ((__HANDLE__)->Config.PlaneSize))) * \
338 ((__HANDLE__)->Config.BlockSize)))
339
345#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
346
352#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
353#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
354#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
355#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
356
362#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */
363#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
364
381#endif /* FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3 */
382
383#ifdef __cplusplus
384}
385#endif
386
387#endif /* STM32F4xx_HAL_NAND_H */
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition stm32f4xx_hal_def.h:39
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition stm32f4xx_hal_def.h:50