STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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Macros
HAL ETH Aliased Defines maintained for legacy purpose

Macros

#define VLAN_TAG   ETH_VLAN_TAG
 
#define MIN_ETH_PAYLOAD   ETH_MIN_ETH_PAYLOAD
 
#define MAX_ETH_PAYLOAD   ETH_MAX_ETH_PAYLOAD
 
#define JUMBO_FRAME_PAYLOAD   ETH_JUMBO_FRAME_PAYLOAD
 
#define MACMIIAR_CR_MASK   ETH_MACMIIAR_CR_MASK
 
#define MACCR_CLEAR_MASK   ETH_MACCR_CLEAR_MASK
 
#define MACFCR_CLEAR_MASK   ETH_MACFCR_CLEAR_MASK
 
#define DMAOMR_CLEAR_MASK   ETH_DMAOMR_CLEAR_MASK
 
#define ETH_MMCCR   0x00000100U
 
#define ETH_MMCRIR   0x00000104U
 
#define ETH_MMCTIR   0x00000108U
 
#define ETH_MMCRIMR   0x0000010CU
 
#define ETH_MMCTIMR   0x00000110U
 
#define ETH_MMCTGFSCCR   0x0000014CU
 
#define ETH_MMCTGFMSCCR   0x00000150U
 
#define ETH_MMCTGFCR   0x00000168U
 
#define ETH_MMCRFCECR   0x00000194U
 
#define ETH_MMCRFAECR   0x00000198U
 
#define ETH_MMCRGUFCR   0x000001C4U
 
#define ETH_MAC_TXFIFO_FULL   0x02000000U /* Tx FIFO full */
 
#define ETH_MAC_TXFIFONOT_EMPTY   0x01000000U /* Tx FIFO not empty */
 
#define ETH_MAC_TXFIFO_WRITE_ACTIVE   0x00400000U /* Tx FIFO write active */
 
#define ETH_MAC_TXFIFO_IDLE   0x00000000U /* Tx FIFO read status: Idle */
 
#define ETH_MAC_TXFIFO_READ
 
#define ETH_MAC_TXFIFO_WAITING
 
#define ETH_MAC_TXFIFO_WRITING
 
#define ETH_MAC_TRANSMISSION_PAUSE   0x00080000U /* MAC transmitter in pause */
 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE   0x00000000U /* MAC transmit frame controller: Idle */
 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING
 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF
 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING
 
#define ETH_MAC_MII_TRANSMIT_ACTIVE   0x00010000U /* MAC MII transmit engine active */
 
#define ETH_MAC_RXFIFO_EMPTY   0x00000000U /* Rx FIFO fill level: empty */
 
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD
 
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD
 
#define ETH_MAC_RXFIFO_FULL   0x00000300U /* Rx FIFO fill level: full */
 
#define ETH_MAC_READCONTROLLER_IDLE   0x00000000U /* Rx FIFO read controller IDLE state */
 
#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U /* Rx FIFO read controller Reading frame data */
 
#define ETH_MAC_READCONTROLLER_READING_STATUS
 
#define ETH_MAC_READCONTROLLER_FLUSHING
 
#define ETH_MAC_RXFIFO_WRITE_ACTIVE   0x00000010U /* Rx FIFO write controller active */
 
#define ETH_MAC_SMALL_FIFO_NOTACTIVE   0x00000000U /* MAC small FIFO read / write controllers not active */
 
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE   0x00000002U /* MAC small FIFO read controller active */
 
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE   0x00000004U /* MAC small FIFO write controller active */
 
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE   0x00000006U /* MAC small FIFO read / write controllers active */
 
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U /* MAC MII receive protocol engine active */
 
#define ETH_TxPacketConfig   ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
 

Detailed Description

Macro Definition Documentation

◆ VLAN_TAG

#define VLAN_TAG   ETH_VLAN_TAG

#include <stm32_hal_legacy.h>

Definition at line 1546 of file stm32_hal_legacy.h.

◆ MIN_ETH_PAYLOAD

#define MIN_ETH_PAYLOAD   ETH_MIN_ETH_PAYLOAD

#include <stm32_hal_legacy.h>

Definition at line 1547 of file stm32_hal_legacy.h.

◆ MAX_ETH_PAYLOAD

#define MAX_ETH_PAYLOAD   ETH_MAX_ETH_PAYLOAD

#include <stm32_hal_legacy.h>

Definition at line 1548 of file stm32_hal_legacy.h.

◆ JUMBO_FRAME_PAYLOAD

#define JUMBO_FRAME_PAYLOAD   ETH_JUMBO_FRAME_PAYLOAD

#include <stm32_hal_legacy.h>

Definition at line 1549 of file stm32_hal_legacy.h.

◆ MACMIIAR_CR_MASK

#define MACMIIAR_CR_MASK   ETH_MACMIIAR_CR_MASK

#include <stm32_hal_legacy.h>

Definition at line 1550 of file stm32_hal_legacy.h.

◆ MACCR_CLEAR_MASK

#define MACCR_CLEAR_MASK   ETH_MACCR_CLEAR_MASK

#include <stm32_hal_legacy.h>

Definition at line 1551 of file stm32_hal_legacy.h.

◆ MACFCR_CLEAR_MASK

#define MACFCR_CLEAR_MASK   ETH_MACFCR_CLEAR_MASK

#include <stm32_hal_legacy.h>

Definition at line 1552 of file stm32_hal_legacy.h.

◆ DMAOMR_CLEAR_MASK

#define DMAOMR_CLEAR_MASK   ETH_DMAOMR_CLEAR_MASK

#include <stm32_hal_legacy.h>

Definition at line 1553 of file stm32_hal_legacy.h.

◆ ETH_MMCCR

#define ETH_MMCCR   0x00000100U

#include <stm32_hal_legacy.h>

Definition at line 1555 of file stm32_hal_legacy.h.

◆ ETH_MMCRIR

#define ETH_MMCRIR   0x00000104U

#include <stm32_hal_legacy.h>

Definition at line 1556 of file stm32_hal_legacy.h.

◆ ETH_MMCTIR

#define ETH_MMCTIR   0x00000108U

#include <stm32_hal_legacy.h>

Definition at line 1557 of file stm32_hal_legacy.h.

◆ ETH_MMCRIMR

#define ETH_MMCRIMR   0x0000010CU

#include <stm32_hal_legacy.h>

Definition at line 1558 of file stm32_hal_legacy.h.

◆ ETH_MMCTIMR

#define ETH_MMCTIMR   0x00000110U

#include <stm32_hal_legacy.h>

Definition at line 1559 of file stm32_hal_legacy.h.

◆ ETH_MMCTGFSCCR

#define ETH_MMCTGFSCCR   0x0000014CU

#include <stm32_hal_legacy.h>

Definition at line 1560 of file stm32_hal_legacy.h.

◆ ETH_MMCTGFMSCCR

#define ETH_MMCTGFMSCCR   0x00000150U

#include <stm32_hal_legacy.h>

Definition at line 1561 of file stm32_hal_legacy.h.

◆ ETH_MMCTGFCR

#define ETH_MMCTGFCR   0x00000168U

#include <stm32_hal_legacy.h>

Definition at line 1562 of file stm32_hal_legacy.h.

◆ ETH_MMCRFCECR

#define ETH_MMCRFCECR   0x00000194U

#include <stm32_hal_legacy.h>

Definition at line 1563 of file stm32_hal_legacy.h.

◆ ETH_MMCRFAECR

#define ETH_MMCRFAECR   0x00000198U

#include <stm32_hal_legacy.h>

Definition at line 1564 of file stm32_hal_legacy.h.

◆ ETH_MMCRGUFCR

#define ETH_MMCRGUFCR   0x000001C4U

#include <stm32_hal_legacy.h>

Definition at line 1565 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFO_FULL

#define ETH_MAC_TXFIFO_FULL   0x02000000U /* Tx FIFO full */

#include <stm32_hal_legacy.h>

Definition at line 1567 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFONOT_EMPTY

#define ETH_MAC_TXFIFONOT_EMPTY   0x01000000U /* Tx FIFO not empty */

#include <stm32_hal_legacy.h>

Definition at line 1568 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFO_WRITE_ACTIVE

#define ETH_MAC_TXFIFO_WRITE_ACTIVE   0x00400000U /* Tx FIFO write active */

#include <stm32_hal_legacy.h>

Definition at line 1569 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFO_IDLE

#define ETH_MAC_TXFIFO_IDLE   0x00000000U /* Tx FIFO read status: Idle */

#include <stm32_hal_legacy.h>

Definition at line 1570 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFO_READ

#define ETH_MAC_TXFIFO_READ

#include <stm32_hal_legacy.h>

Value:
0x00100000U /* Tx FIFO read status: Read (transferring data to
the MAC transmitter) */

Definition at line 1571 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFO_WAITING

#define ETH_MAC_TXFIFO_WAITING

#include <stm32_hal_legacy.h>

Value:
0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
MAC transmitter */

Definition at line 1572 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFO_WRITING

#define ETH_MAC_TXFIFO_WRITING

#include <stm32_hal_legacy.h>

Value:
0x00300000U /* Tx FIFO read status: Writing the received TxStatus
or flushing the TxFIFO */

Definition at line 1573 of file stm32_hal_legacy.h.

◆ ETH_MAC_TRANSMISSION_PAUSE

#define ETH_MAC_TRANSMISSION_PAUSE   0x00080000U /* MAC transmitter in pause */

#include <stm32_hal_legacy.h>

Definition at line 1574 of file stm32_hal_legacy.h.

◆ ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE

#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE   0x00000000U /* MAC transmit frame controller: Idle */

#include <stm32_hal_legacy.h>

Definition at line 1575 of file stm32_hal_legacy.h.

◆ ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING

#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING

#include <stm32_hal_legacy.h>

Value:
0x00020000U /* MAC transmit frame controller: Waiting for Status
of previous frame or IFG/backoff period to be over */

Definition at line 1576 of file stm32_hal_legacy.h.

◆ ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF

#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF

#include <stm32_hal_legacy.h>

Value:
0x00040000U /* MAC transmit frame controller: Generating and
transmitting a Pause control frame (in full duplex mode) */

Definition at line 1577 of file stm32_hal_legacy.h.

◆ ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING

#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING

#include <stm32_hal_legacy.h>

Value:
0x00060000U /* MAC transmit frame controller: Transferring input
frame for transmission */

Definition at line 1578 of file stm32_hal_legacy.h.

◆ ETH_MAC_MII_TRANSMIT_ACTIVE

#define ETH_MAC_MII_TRANSMIT_ACTIVE   0x00010000U /* MAC MII transmit engine active */

#include <stm32_hal_legacy.h>

Definition at line 1579 of file stm32_hal_legacy.h.

◆ ETH_MAC_RXFIFO_EMPTY

#define ETH_MAC_RXFIFO_EMPTY   0x00000000U /* Rx FIFO fill level: empty */

#include <stm32_hal_legacy.h>

Definition at line 1580 of file stm32_hal_legacy.h.

◆ ETH_MAC_RXFIFO_BELOW_THRESHOLD

#define ETH_MAC_RXFIFO_BELOW_THRESHOLD

#include <stm32_hal_legacy.h>

Value:
0x00000100U /* Rx FIFO fill level: fill-level below flow-control
de-activate threshold */

Definition at line 1581 of file stm32_hal_legacy.h.

◆ ETH_MAC_RXFIFO_ABOVE_THRESHOLD

#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD

#include <stm32_hal_legacy.h>

Value:
0x00000200U /* Rx FIFO fill level: fill-level above flow-control
activate threshold */

Definition at line 1582 of file stm32_hal_legacy.h.

◆ ETH_MAC_RXFIFO_FULL

#define ETH_MAC_RXFIFO_FULL   0x00000300U /* Rx FIFO fill level: full */

#include <stm32_hal_legacy.h>

Definition at line 1583 of file stm32_hal_legacy.h.

◆ ETH_MAC_READCONTROLLER_IDLE

#define ETH_MAC_READCONTROLLER_IDLE   0x00000000U /* Rx FIFO read controller IDLE state */

#include <stm32_hal_legacy.h>

Definition at line 1586 of file stm32_hal_legacy.h.

◆ ETH_MAC_READCONTROLLER_READING_DATA

#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U /* Rx FIFO read controller Reading frame data */

#include <stm32_hal_legacy.h>

Definition at line 1587 of file stm32_hal_legacy.h.

◆ ETH_MAC_READCONTROLLER_READING_STATUS

#define ETH_MAC_READCONTROLLER_READING_STATUS

#include <stm32_hal_legacy.h>

Value:
0x00000040U /* Rx FIFO read controller Reading frame status
(or time-stamp) */

Definition at line 1588 of file stm32_hal_legacy.h.

◆ ETH_MAC_READCONTROLLER_FLUSHING

#define ETH_MAC_READCONTROLLER_FLUSHING

#include <stm32_hal_legacy.h>

Value:
0x00000060U /* Rx FIFO read controller Flushing the frame data and
status */

Definition at line 1590 of file stm32_hal_legacy.h.

◆ ETH_MAC_RXFIFO_WRITE_ACTIVE

#define ETH_MAC_RXFIFO_WRITE_ACTIVE   0x00000010U /* Rx FIFO write controller active */

#include <stm32_hal_legacy.h>

Definition at line 1591 of file stm32_hal_legacy.h.

◆ ETH_MAC_SMALL_FIFO_NOTACTIVE

#define ETH_MAC_SMALL_FIFO_NOTACTIVE   0x00000000U /* MAC small FIFO read / write controllers not active */

#include <stm32_hal_legacy.h>

Definition at line 1592 of file stm32_hal_legacy.h.

◆ ETH_MAC_SMALL_FIFO_READ_ACTIVE

#define ETH_MAC_SMALL_FIFO_READ_ACTIVE   0x00000002U /* MAC small FIFO read controller active */

#include <stm32_hal_legacy.h>

Definition at line 1593 of file stm32_hal_legacy.h.

◆ ETH_MAC_SMALL_FIFO_WRITE_ACTIVE

#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE   0x00000004U /* MAC small FIFO write controller active */

#include <stm32_hal_legacy.h>

Definition at line 1594 of file stm32_hal_legacy.h.

◆ ETH_MAC_SMALL_FIFO_RW_ACTIVE

#define ETH_MAC_SMALL_FIFO_RW_ACTIVE   0x00000006U /* MAC small FIFO read / write controllers active */

#include <stm32_hal_legacy.h>

Definition at line 1595 of file stm32_hal_legacy.h.

◆ ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE

#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U /* MAC MII receive protocol engine active */

#include <stm32_hal_legacy.h>

Definition at line 1596 of file stm32_hal_legacy.h.

◆ ETH_TxPacketConfig

#define ETH_TxPacketConfig   ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */

#include <stm32_hal_legacy.h>

Definition at line 1598 of file stm32_hal_legacy.h.