Initialization and de-initialization functions

Initialization and de-initialization functions. More...

Collaboration diagram for Initialization and de-initialization functions:

Functions
void	HAL_PWR_DeInit (void)
	Deinitializes the HAL PWR peripheral registers to their default reset values.
void	HAL_PWR_EnableBkUpAccess (void)
	Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).
void	HAL_PWR_DisableBkUpAccess (void)
	Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      After reset, the backup domain (RTC registers, RTC backup data 
      registers and backup SRAM) is protected against possible unwanted 
      write accesses. 
      To enable access to the RTC Domain and RTC registers, proceed as follows:
        (+) Enable the Power Controller (PWR) APB1 interface clock using the
            __HAL_RCC_PWR_CLK_ENABLE() macro.
        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.

Function Documentation

HAL_PWR_DeInit()

void HAL_PWR_DeInit

(

void

)

#include <stm32f4xx_hal_pwr.h>

Deinitializes the HAL PWR peripheral registers to their default reset values.

Return values

None

Definition at line 90 of file stm32f4xx_hal_pwr.c.

References __HAL_RCC_PWR_FORCE_RESET, and __HAL_RCC_PWR_RELEASE_RESET.

HAL_PWR_EnableBkUpAccess()

void HAL_PWR_EnableBkUpAccess

(

void

)

#include <stm32f4xx_hal_pwr.h>

Enables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note

If the HSE divided by 2, 3, ..31 is used as the RTC clock, the Backup Domain Access should be kept enabled.

The following sequence is required to bypass the delay between DBP bit programming and the effective enabling of the backup domain. Please check the Errata Sheet for more details under "Possible delay in backup domain protection disabling/enabling after programming the DBP bit" section.

Return values

None

Definition at line 108 of file stm32f4xx_hal_pwr.c.

References CR_DBP_BB, and UNUSED.

HAL_PWR_DisableBkUpAccess()

void HAL_PWR_DisableBkUpAccess

(

void

)

#include <stm32f4xx_hal_pwr.h>

Disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

Note

If the HSE divided by 2, 3, ..31 is used as the RTC clock, the Backup Domain Access should be kept enabled.

The following sequence is required to bypass the delay between DBP bit programming and the effective disabling of the backup domain. Please check the Errata Sheet for more details under "Possible delay in backup domain protection disabling/enabling after programming the DBP bit" section.

Return values

None

Definition at line 128 of file stm32f4xx_hal_pwr.c.

References CR_DBP_BB, and UNUSED.