STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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stm32f4xx_hal_rcc.h
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1
18/* Define to prevent recursive inclusion -------------------------------------*/
19#ifndef __STM32F4xx_HAL_RCC_H
20#define __STM32F4xx_HAL_RCC_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/* Includes ------------------------------------------------------------------*/
27#include "stm32f4xx_hal_def.h"
28
29/* Include RCC HAL Extended module */
30/* (include on top of file since RCC structures are defined in extended file) */
31#include "stm32f4xx_hal_rcc_ex.h"
32
41/* Exported types ------------------------------------------------------------*/
49typedef struct
50{
51 uint32_t OscillatorType;
54 uint32_t HSEState;
57 uint32_t LSEState;
60 uint32_t HSIState;
63 uint32_t HSICalibrationValue;
66 uint32_t LSIState;
69 RCC_PLLInitTypeDef PLL;
70} RCC_OscInitTypeDef;
71
75typedef struct
76{
77 uint32_t ClockType;
80 uint32_t SYSCLKSource;
83 uint32_t AHBCLKDivider;
86 uint32_t APB1CLKDivider;
89 uint32_t APB2CLKDivider;
92} RCC_ClkInitTypeDef;
93
98/* Exported constants --------------------------------------------------------*/
106#define RCC_OSCILLATORTYPE_NONE 0x00000000U
107#define RCC_OSCILLATORTYPE_HSE 0x00000001U
108#define RCC_OSCILLATORTYPE_HSI 0x00000002U
109#define RCC_OSCILLATORTYPE_LSE 0x00000004U
110#define RCC_OSCILLATORTYPE_LSI 0x00000008U
118#define RCC_HSE_OFF 0x00000000U
119#define RCC_HSE_ON RCC_CR_HSEON
120#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
128#define RCC_LSE_OFF 0x00000000U
129#define RCC_LSE_ON RCC_BDCR_LSEON
130#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
138#define RCC_HSI_OFF ((uint8_t)0x00)
139#define RCC_HSI_ON ((uint8_t)0x01)
140
141#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
149#define RCC_LSI_OFF ((uint8_t)0x00)
150#define RCC_LSI_ON ((uint8_t)0x01)
158#define RCC_PLL_NONE ((uint8_t)0x00)
159#define RCC_PLL_OFF ((uint8_t)0x01)
160#define RCC_PLL_ON ((uint8_t)0x02)
168#define RCC_PLLP_DIV2 0x00000002U
169#define RCC_PLLP_DIV4 0x00000004U
170#define RCC_PLLP_DIV6 0x00000006U
171#define RCC_PLLP_DIV8 0x00000008U
179#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
180#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
188#define RCC_CLOCKTYPE_SYSCLK 0x00000001U
189#define RCC_CLOCKTYPE_HCLK 0x00000002U
190#define RCC_CLOCKTYPE_PCLK1 0x00000004U
191#define RCC_CLOCKTYPE_PCLK2 0x00000008U
201#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
202#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
203#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
204#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
214#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
215#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
216#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
217#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1))
225#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
226#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
227#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
228#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
229#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
230#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
231#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
232#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
233#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
241#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
242#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
243#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
244#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
245#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
253#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
254#define RCC_RTCCLKSOURCE_LSE 0x00000100U
255#define RCC_RTCCLKSOURCE_LSI 0x00000200U
256#define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U
257#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
258#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
259#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
260#define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
261#define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
262#define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
263#define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
264#define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
265#define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
266#define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
267#define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
268#define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
269#define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
270#define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
271#define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
272#define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
273#define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
274#define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
275#define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
276#define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
277#define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
278#define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
279#define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
280#define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
281#define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
282#define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
283#define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
284#define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
285#define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
286#define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
294#define RCC_MCO1 0x00000000U
295#define RCC_MCO2 0x00000001U
303#define RCC_MCO1SOURCE_HSI 0x00000000U
304#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
305#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
306#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
314#define RCC_MCODIV_1 0x00000000U
315#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
316#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
317#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
318#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
326#define RCC_IT_LSIRDY ((uint8_t)0x01)
327#define RCC_IT_LSERDY ((uint8_t)0x02)
328#define RCC_IT_HSIRDY ((uint8_t)0x04)
329#define RCC_IT_HSERDY ((uint8_t)0x08)
330#define RCC_IT_PLLRDY ((uint8_t)0x10)
331#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
332#define RCC_IT_CSS ((uint8_t)0x80)
346/* Flags in the CR register */
347#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
348#define RCC_FLAG_HSERDY ((uint8_t)0x31)
349#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
350#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
351
352/* Flags in the BDCR register */
353#define RCC_FLAG_LSERDY ((uint8_t)0x41)
354
355/* Flags in the CSR register */
356#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
357#define RCC_FLAG_BORRST ((uint8_t)0x79)
358#define RCC_FLAG_PINRST ((uint8_t)0x7A)
359#define RCC_FLAG_PORRST ((uint8_t)0x7B)
360#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
361#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
362#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
363#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
372/* Exported macro ------------------------------------------------------------*/
384#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
385 __IO uint32_t tmpreg = 0x00U; \
386 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
387 /* Delay after an RCC peripheral clock enabling */ \
388 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
389 UNUSED(tmpreg); \
390 } while(0U)
391#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
392 __IO uint32_t tmpreg = 0x00U; \
393 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
394 /* Delay after an RCC peripheral clock enabling */ \
395 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
396 UNUSED(tmpreg); \
397 } while(0U)
398#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
399 __IO uint32_t tmpreg = 0x00U; \
400 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
401 /* Delay after an RCC peripheral clock enabling */ \
402 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
403 UNUSED(tmpreg); \
404 } while(0U)
405#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
406 __IO uint32_t tmpreg = 0x00U; \
407 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
408 /* Delay after an RCC peripheral clock enabling */ \
409 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
410 UNUSED(tmpreg); \
411 } while(0U)
412#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
413 __IO uint32_t tmpreg = 0x00U; \
414 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
415 /* Delay after an RCC peripheral clock enabling */ \
416 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
417 UNUSED(tmpreg); \
418 } while(0U)
419#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
420 __IO uint32_t tmpreg = 0x00U; \
421 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
422 /* Delay after an RCC peripheral clock enabling */ \
423 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
424 UNUSED(tmpreg); \
425 } while(0U)
426
427#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
428#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
429#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
430#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
431#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
432#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
444#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
445#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
446#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
447#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
448#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
449#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
450
451#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
452#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
453#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
454#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
455#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
456#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
468#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
469 __IO uint32_t tmpreg = 0x00U; \
470 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
471 /* Delay after an RCC peripheral clock enabling */ \
472 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
473 UNUSED(tmpreg); \
474 } while(0U)
475#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
476 __IO uint32_t tmpreg = 0x00U; \
477 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
478 /* Delay after an RCC peripheral clock enabling */ \
479 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
480 UNUSED(tmpreg); \
481 } while(0U)
482#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
483 __IO uint32_t tmpreg = 0x00U; \
484 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
485 /* Delay after an RCC peripheral clock enabling */ \
486 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
487 UNUSED(tmpreg); \
488 } while(0U)
489#define __HAL_RCC_USART2_CLK_ENABLE() do { \
490 __IO uint32_t tmpreg = 0x00U; \
491 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
492 /* Delay after an RCC peripheral clock enabling */ \
493 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
494 UNUSED(tmpreg); \
495 } while(0U)
496#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
497 __IO uint32_t tmpreg = 0x00U; \
498 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
499 /* Delay after an RCC peripheral clock enabling */ \
500 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
501 UNUSED(tmpreg); \
502 } while(0U)
503#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
504 __IO uint32_t tmpreg = 0x00U; \
505 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
506 /* Delay after an RCC peripheral clock enabling */ \
507 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
508 UNUSED(tmpreg); \
509 } while(0U)
510#define __HAL_RCC_PWR_CLK_ENABLE() do { \
511 __IO uint32_t tmpreg = 0x00U; \
512 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
513 /* Delay after an RCC peripheral clock enabling */ \
514 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
515 UNUSED(tmpreg); \
516 } while(0U)
517
518#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
519#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
520#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
521#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
522#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
523#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
524#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
536#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
537#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
538#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
539#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
540#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
541#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
542#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
543
544#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
545#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
546#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
547#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
548#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
549#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
550#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
562#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
563 __IO uint32_t tmpreg = 0x00U; \
564 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
565 /* Delay after an RCC peripheral clock enabling */ \
566 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
567 UNUSED(tmpreg); \
568 } while(0U)
569#define __HAL_RCC_USART1_CLK_ENABLE() do { \
570 __IO uint32_t tmpreg = 0x00U; \
571 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
572 /* Delay after an RCC peripheral clock enabling */ \
573 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
574 UNUSED(tmpreg); \
575 } while(0U)
576#define __HAL_RCC_USART6_CLK_ENABLE() do { \
577 __IO uint32_t tmpreg = 0x00U; \
578 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
579 /* Delay after an RCC peripheral clock enabling */ \
580 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
581 UNUSED(tmpreg); \
582 } while(0U)
583#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
584 __IO uint32_t tmpreg = 0x00U; \
585 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
586 /* Delay after an RCC peripheral clock enabling */ \
587 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
588 UNUSED(tmpreg); \
589 } while(0U)
590#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
591 __IO uint32_t tmpreg = 0x00U; \
592 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
593 /* Delay after an RCC peripheral clock enabling */ \
594 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
595 UNUSED(tmpreg); \
596 } while(0U)
597#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
598 __IO uint32_t tmpreg = 0x00U; \
599 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
600 /* Delay after an RCC peripheral clock enabling */ \
601 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
602 UNUSED(tmpreg); \
603 } while(0U)
604#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
605 __IO uint32_t tmpreg = 0x00U; \
606 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
607 /* Delay after an RCC peripheral clock enabling */ \
608 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
609 UNUSED(tmpreg); \
610 } while(0U)
611#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
612 __IO uint32_t tmpreg = 0x00U; \
613 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
614 /* Delay after an RCC peripheral clock enabling */ \
615 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
616 UNUSED(tmpreg); \
617 } while(0U)
618
619#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
620#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
621#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
622#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
623#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
624#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
625#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
626#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
638#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
639#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
640#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
641#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
642#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
643#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
644#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
645#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
646
647#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
648#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
649#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
650#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
651#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
652#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
653#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
654#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
663#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
664#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
665#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
666#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
667#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
668#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
669
670#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
671#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
672#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
673#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
674#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
675#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
676#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
685#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
686#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
687#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
688#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
689#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
690#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
691#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
692
693#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
694#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
695#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
696#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
697#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
698#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
699#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
700#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
709#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
710#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
711#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
712#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
713#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
714#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
715#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
716#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
717
718#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
719#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
720#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
721#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
722#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
723#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
724#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
725#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
726#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
739#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
740#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
741#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
742#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
743#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
744#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
745
746#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
747#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
748#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
749#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
750#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
751#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
764#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
765#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
766#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
767#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
768#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
769#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
770#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
771
772#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
773#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
774#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
775#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
776#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
777#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
778#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
791#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
792#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
793#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
794#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
795#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
796#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
797#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
798#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
799
800#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
801#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
802#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
803#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
804#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
805#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
806#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
807#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
831#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
832#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
833
841#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
842 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
859#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
860#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
890#define __HAL_RCC_HSE_CONFIG(__STATE__) \
891 do { \
892 if ((__STATE__) == RCC_HSE_ON) \
893 { \
894 SET_BIT(RCC->CR, RCC_CR_HSEON); \
895 } \
896 else if ((__STATE__) == RCC_HSE_BYPASS) \
897 { \
898 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
899 SET_BIT(RCC->CR, RCC_CR_HSEON); \
900 } \
901 else \
902 { \
903 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
904 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
905 } \
906 } while(0U)
933#define __HAL_RCC_LSE_CONFIG(__STATE__) \
934 do { \
935 if((__STATE__) == RCC_LSE_ON) \
936 { \
937 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
938 } \
939 else if((__STATE__) == RCC_LSE_BYPASS) \
940 { \
941 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
942 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
943 } \
944 else \
945 { \
946 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
947 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
948 } \
949 } while(0U)
961#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
962#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
963
985#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
986 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
987
988#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
989 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
990 } while(0U)
991
999#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
1000
1006#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
1007
1013#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
1014#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
1030#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
1031#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
1032
1041#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
1042
1052#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
1070#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
1071
1081#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
1082
1089#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
1113#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1114 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1115
1134#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1135 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
1156#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1157
1169#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1170
1183#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1184
1197#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1198
1202#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1203
1222#define RCC_FLAG_MASK ((uint8_t)0x1FU)
1223#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U)\
1224 == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) &\
1225 (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
1226
1235/* Exported functions --------------------------------------------------------*/
1243/* Initialization and de-initialization functions ******************************/
1244HAL_StatusTypeDef HAL_RCC_DeInit(void);
1245HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1246HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1254/* Peripheral Control functions ************************************************/
1255void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1256void HAL_RCC_EnableCSS(void);
1257void HAL_RCC_DisableCSS(void);
1258uint32_t HAL_RCC_GetSysClockFreq(void);
1259uint32_t HAL_RCC_GetHCLKFreq(void);
1260uint32_t HAL_RCC_GetPCLK1Freq(void);
1261uint32_t HAL_RCC_GetPCLK2Freq(void);
1262void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1263void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1264
1265/* CSS NMI IRQ handler */
1266void HAL_RCC_NMI_IRQHandler(void);
1267
1268/* User Callbacks in non blocking mode (IT mode) */
1269void HAL_RCC_CSSCallback(void);
1270
1279/* Private types -------------------------------------------------------------*/
1280/* Private variables ---------------------------------------------------------*/
1281/* Private constants ---------------------------------------------------------*/
1290#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
1291/* --- CR Register --- */
1292/* Alias word address of HSION bit */
1293#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
1294#define RCC_HSION_BIT_NUMBER 0x00U
1295#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
1296/* Alias word address of CSSON bit */
1297#define RCC_CSSON_BIT_NUMBER 0x13U
1298#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
1299/* Alias word address of PLLON bit */
1300#define RCC_PLLON_BIT_NUMBER 0x18U
1301#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
1302
1303/* --- BDCR Register --- */
1304/* Alias word address of RTCEN bit */
1305#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
1306#define RCC_RTCEN_BIT_NUMBER 0x0FU
1307#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
1308/* Alias word address of BDRST bit */
1309#define RCC_BDRST_BIT_NUMBER 0x10U
1310#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
1311
1312/* --- CSR Register --- */
1313/* Alias word address of LSION bit */
1314#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
1315#define RCC_LSION_BIT_NUMBER 0x00U
1316#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
1317
1318/* CR register byte 3 (Bits[23:16]) base address */
1319#define RCC_CR_BYTE2_ADDRESS 0x40023802U
1320
1321/* CIR register byte 2 (Bits[15:8]) base address */
1322#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
1323
1324/* CIR register byte 3 (Bits[23:16]) base address */
1325#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
1326
1327/* BDCR register base address */
1328#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
1329
1330#define RCC_DBP_TIMEOUT_VALUE 2U
1331#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
1332
1333#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
1334#define HSI_TIMEOUT_VALUE 2U /* 2 ms */
1335#define LSI_TIMEOUT_VALUE 2U /* 2 ms */
1336#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
1337
1346/* Private macros ------------------------------------------------------------*/
1354#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
1355
1356#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
1357 ((HSE) == RCC_HSE_BYPASS))
1358
1359#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
1360 ((LSE) == RCC_LSE_BYPASS))
1361
1362#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
1363
1364#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
1365
1366#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
1367
1368#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
1369 ((SOURCE) == RCC_PLLSOURCE_HSE))
1370
1371#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
1372 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
1373 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
1374 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
1375
1376#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
1377 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
1378 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
1379 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
1380 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
1381 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
1382 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
1383 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
1384 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
1385 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
1386 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
1387 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
1388 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
1389 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
1390 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
1391 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
1392 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
1393 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
1394 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
1395 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
1396 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
1397 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
1398 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
1399 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
1400 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
1401 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
1402 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
1403 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
1404 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
1405 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
1406 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
1407 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
1408
1409#define IS_RCC_PLLM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U))
1410
1411#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
1412
1413#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
1414
1415#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
1416 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
1417 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
1418 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
1419 ((HCLK) == RCC_SYSCLK_DIV512))
1420
1421#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
1422
1423#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
1424 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
1425 ((PCLK) == RCC_HCLK_DIV16))
1426
1427#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
1428
1429#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
1430 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
1431
1432#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
1433 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
1434 ((DIV) == RCC_MCODIV_5))
1435#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
1436
1453#ifdef __cplusplus
1454}
1455#endif
1456
1457#endif /* __STM32F4xx_HAL_RCC_H */
1458
HAL_RCC_DeInit
HAL_StatusTypeDef HAL_RCC_DeInit(void)
Resets the RCC clock configuration to the default reset state.
Definition stm32f4xx_hal_rcc.c:200
HAL_RCC_OscConfig
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
Definition stm32f4xx_hal_rcc.c:219
HAL_RCC_ClockConfig
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkIn...
Definition stm32f4xx_hal_rcc.c:591
HAL_RCC_NMI_IRQHandler
void HAL_RCC_NMI_IRQHandler(void)
This function handles the RCC CSS interrupt request.
Definition stm32f4xx_hal_rcc.c:1084
HAL_RCC_GetHCLKFreq
uint32_t HAL_RCC_GetHCLKFreq(void)
Returns the HCLK frequency.
Definition stm32f4xx_hal_rcc.c:943
HAL_RCC_GetOscConfig
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
Definition stm32f4xx_hal_rcc.c:979
HAL_RCC_MCOConfig
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
Definition stm32f4xx_hal_rcc.c:775
HAL_RCC_EnableCSS
void HAL_RCC_EnableCSS(void)
Enables the Clock Security System.
Definition stm32f4xx_hal_rcc.c:841
HAL_RCC_GetSysClockFreq
uint32_t HAL_RCC_GetSysClockFreq(void)
Returns the SYSCLK frequency.
Definition stm32f4xx_hal_rcc.c:885
HAL_RCC_GetPCLK1Freq
uint32_t HAL_RCC_GetPCLK1Freq(void)
Returns the PCLK1 frequency.
Definition stm32f4xx_hal_rcc.c:954
HAL_RCC_GetPCLK2Freq
uint32_t HAL_RCC_GetPCLK2Freq(void)
Returns the PCLK2 frequency.
Definition stm32f4xx_hal_rcc.c:966
HAL_RCC_GetClockConfig
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
Definition stm32f4xx_hal_rcc.c:1058
HAL_RCC_DisableCSS
void HAL_RCC_DisableCSS(void)
Disables the Clock Security System.
Definition stm32f4xx_hal_rcc.c:850
HAL_RCC_CSSCallback
void HAL_RCC_CSSCallback(void)
RCC Clock Security System interrupt callback.
Definition stm32f4xx_hal_rcc.c:1101
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition stm32f4xx_hal_def.h:39
stm32f4xx_hal_rcc_ex.h
Header file of RCC HAL Extension module.
RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition.
Definition stm32f4xx_hal_rcc.h:76
RCC_ClkInitTypeDef::APB1CLKDivider
uint32_t APB1CLKDivider
Definition stm32f4xx_hal_rcc.h:86
RCC_ClkInitTypeDef::SYSCLKSource
uint32_t SYSCLKSource
Definition stm32f4xx_hal_rcc.h:80
RCC_ClkInitTypeDef::ClockType
uint32_t ClockType
Definition stm32f4xx_hal_rcc.h:77
RCC_ClkInitTypeDef::APB2CLKDivider
uint32_t APB2CLKDivider
Definition stm32f4xx_hal_rcc.h:89
RCC_ClkInitTypeDef::AHBCLKDivider
uint32_t AHBCLKDivider
Definition stm32f4xx_hal_rcc.h:83
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.
Definition stm32f4xx_hal_rcc.h:50
RCC_OscInitTypeDef::HSIState
uint32_t HSIState
Definition stm32f4xx_hal_rcc.h:60
RCC_OscInitTypeDef::LSEState
uint32_t LSEState
Definition stm32f4xx_hal_rcc.h:57
RCC_OscInitTypeDef::HSEState
uint32_t HSEState
Definition stm32f4xx_hal_rcc.h:54
RCC_OscInitTypeDef::LSIState
uint32_t LSIState
Definition stm32f4xx_hal_rcc.h:66
RCC_OscInitTypeDef::HSICalibrationValue
uint32_t HSICalibrationValue
Definition stm32f4xx_hal_rcc.h:63
RCC_OscInitTypeDef::PLL
RCC_PLLInitTypeDef PLL
Definition stm32f4xx_hal_rcc.h:69
RCC_OscInitTypeDef::OscillatorType
uint32_t OscillatorType
Definition stm32f4xx_hal_rcc.h:51
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition stm32f4xx_hal_rcc_ex.h:46