STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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Macros
AHB1 Peripheral Clock Enable Disable
STM32F4xx_HAL_Driver » RCC » RCC Exported Macros

Enable or disable the AHB1 peripheral clock. More...

Collaboration diagram for AHB1 Peripheral Clock Enable Disable:

Macros

#define __HAL_RCC_GPIOA_CLK_ENABLE()
 
#define __HAL_RCC_GPIOB_CLK_ENABLE()
 
#define __HAL_RCC_GPIOC_CLK_ENABLE()
 
#define __HAL_RCC_GPIOH_CLK_ENABLE()
 
#define __HAL_RCC_DMA1_CLK_ENABLE()
 
#define __HAL_RCC_DMA2_CLK_ENABLE()
 
#define __HAL_RCC_GPIOA_CLK_DISABLE()
 
#define __HAL_RCC_GPIOB_CLK_DISABLE()
 
#define __HAL_RCC_GPIOC_CLK_DISABLE()
 
#define __HAL_RCC_GPIOH_CLK_DISABLE()
 
#define __HAL_RCC_DMA1_CLK_DISABLE()
 
#define __HAL_RCC_DMA2_CLK_DISABLE()
 

Detailed Description

Enable or disable the AHB1 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

◆ __HAL_RCC_GPIOA_CLK_ENABLE

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 384 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_GPIOB_CLK_ENABLE

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 391 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_GPIOC_CLK_ENABLE

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 398 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_GPIOH_CLK_ENABLE

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 405 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_DMA1_CLK_ENABLE

#define __HAL_RCC_DMA1_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 412 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_DMA2_CLK_ENABLE

#define __HAL_RCC_DMA2_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 419 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_GPIOA_CLK_DISABLE

#define __HAL_RCC_GPIOA_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))

Definition at line 427 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_GPIOB_CLK_DISABLE

#define __HAL_RCC_GPIOB_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))

Definition at line 428 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_GPIOC_CLK_DISABLE

#define __HAL_RCC_GPIOC_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))

Definition at line 429 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_GPIOH_CLK_DISABLE

#define __HAL_RCC_GPIOH_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))

Definition at line 430 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_DMA1_CLK_DISABLE

#define __HAL_RCC_DMA1_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))

Definition at line 431 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_DMA2_CLK_DISABLE

#define __HAL_RCC_DMA2_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))

Definition at line 432 of file stm32f4xx_hal_rcc.h.