STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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Macros
APB1 Peripheral Clock Enable Disable
STM32F4xx_HAL_Driver » RCC » RCC Exported Macros

Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Collaboration diagram for APB1 Peripheral Clock Enable Disable:

Macros

#define __HAL_RCC_TIM5_CLK_ENABLE()
 
#define __HAL_RCC_WWDG_CLK_ENABLE()
 
#define __HAL_RCC_SPI2_CLK_ENABLE()
 
#define __HAL_RCC_USART2_CLK_ENABLE()
 
#define __HAL_RCC_I2C1_CLK_ENABLE()
 
#define __HAL_RCC_I2C2_CLK_ENABLE()
 
#define __HAL_RCC_PWR_CLK_ENABLE()
 
#define __HAL_RCC_TIM5_CLK_DISABLE()
 
#define __HAL_RCC_WWDG_CLK_DISABLE()
 
#define __HAL_RCC_SPI2_CLK_DISABLE()
 
#define __HAL_RCC_USART2_CLK_DISABLE()
 
#define __HAL_RCC_I2C1_CLK_DISABLE()
 
#define __HAL_RCC_I2C2_CLK_DISABLE()
 
#define __HAL_RCC_PWR_CLK_DISABLE()
 

Detailed Description

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

◆ __HAL_RCC_TIM5_CLK_ENABLE

#define __HAL_RCC_TIM5_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 468 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_WWDG_CLK_ENABLE

#define __HAL_RCC_WWDG_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 475 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI2_CLK_ENABLE

#define __HAL_RCC_SPI2_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 482 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART2_CLK_ENABLE

#define __HAL_RCC_USART2_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 489 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C1_CLK_ENABLE

#define __HAL_RCC_I2C1_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 496 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C2_CLK_ENABLE

#define __HAL_RCC_I2C2_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 503 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_PWR_CLK_ENABLE

#define __HAL_RCC_PWR_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 510 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_FLASHEx_DisableFlashSleepMode(), HAL_FLASHEx_EnableFlashSleepMode(), HAL_FLASHEx_StartFlashInterfaceClk(), HAL_FLASHEx_StopFlashInterfaceClk(), HAL_PWREx_ControlVoltageScaling(), HAL_PWREx_DisableOverDrive(), HAL_PWREx_EnableOverDrive(), HAL_PWREx_EnterUnderDriveSTOPMode(), HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

◆ __HAL_RCC_TIM5_CLK_DISABLE

#define __HAL_RCC_TIM5_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))

Definition at line 518 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_WWDG_CLK_DISABLE

#define __HAL_RCC_WWDG_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

Definition at line 519 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI2_CLK_DISABLE

#define __HAL_RCC_SPI2_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))

Definition at line 520 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART2_CLK_DISABLE

#define __HAL_RCC_USART2_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

Definition at line 521 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C1_CLK_DISABLE

#define __HAL_RCC_I2C1_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

Definition at line 522 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_I2C2_CLK_DISABLE

#define __HAL_RCC_I2C2_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))

Definition at line 523 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_PWR_CLK_DISABLE

#define __HAL_RCC_PWR_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Definition at line 524 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().