STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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Macros
APB2 Peripheral Clock Enable Disable
STM32F4xx_HAL_Driver » RCC » RCC Exported Macros

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Collaboration diagram for APB2 Peripheral Clock Enable Disable:

Macros

#define __HAL_RCC_TIM1_CLK_ENABLE()
 
#define __HAL_RCC_USART1_CLK_ENABLE()
 
#define __HAL_RCC_USART6_CLK_ENABLE()
 
#define __HAL_RCC_ADC1_CLK_ENABLE()
 
#define __HAL_RCC_SPI1_CLK_ENABLE()
 
#define __HAL_RCC_SYSCFG_CLK_ENABLE()
 
#define __HAL_RCC_TIM9_CLK_ENABLE()
 
#define __HAL_RCC_TIM11_CLK_ENABLE()
 
#define __HAL_RCC_TIM1_CLK_DISABLE()
 
#define __HAL_RCC_USART1_CLK_DISABLE()
 
#define __HAL_RCC_USART6_CLK_DISABLE()
 
#define __HAL_RCC_ADC1_CLK_DISABLE()
 
#define __HAL_RCC_SPI1_CLK_DISABLE()
 
#define __HAL_RCC_SYSCFG_CLK_DISABLE()
 
#define __HAL_RCC_TIM9_CLK_DISABLE()
 
#define __HAL_RCC_TIM11_CLK_DISABLE()
 

Detailed Description

Enable or disable the High Speed APB (APB2) peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

◆ __HAL_RCC_TIM1_CLK_ENABLE

#define __HAL_RCC_TIM1_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 562 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART1_CLK_ENABLE

#define __HAL_RCC_USART1_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 569 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART6_CLK_ENABLE

#define __HAL_RCC_USART6_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 576 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_ADC1_CLK_ENABLE

#define __HAL_RCC_ADC1_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 583 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI1_CLK_ENABLE

#define __HAL_RCC_SPI1_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 590 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SYSCFG_CLK_ENABLE

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 597 of file stm32f4xx_hal_rcc.h.

Referenced by HAL_ETH_Init(), HAL_FMPI2CEx_DisableFastModePlus(), HAL_FMPI2CEx_EnableFastModePlus(), HAL_FMPSMBUSEx_DisableFastModePlus(), HAL_FMPSMBUSEx_EnableFastModePlus(), and HAL_GPIO_Init().

◆ __HAL_RCC_TIM9_CLK_ENABLE

#define __HAL_RCC_TIM9_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 604 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM11_CLK_ENABLE

#define __HAL_RCC_TIM11_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 611 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM1_CLK_DISABLE

#define __HAL_RCC_TIM1_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))

Definition at line 619 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART1_CLK_DISABLE

#define __HAL_RCC_USART1_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

Definition at line 620 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_USART6_CLK_DISABLE

#define __HAL_RCC_USART6_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))

Definition at line 621 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_ADC1_CLK_DISABLE

#define __HAL_RCC_ADC1_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

Definition at line 622 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SPI1_CLK_DISABLE

#define __HAL_RCC_SPI1_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))

Definition at line 623 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_SYSCFG_CLK_DISABLE

#define __HAL_RCC_SYSCFG_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))

Definition at line 624 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM9_CLK_DISABLE

#define __HAL_RCC_TIM9_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))

Definition at line 625 of file stm32f4xx_hal_rcc.h.

◆ __HAL_RCC_TIM11_CLK_DISABLE

#define __HAL_RCC_TIM11_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))

Definition at line 626 of file stm32f4xx_hal_rcc.h.