20#ifndef __STM32F4xx_HAL_CAN_LEGACY_H
21#define __STM32F4xx_HAL_CAN_LEGACY_H
27#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
28 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
29 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
30 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
243#define HAL_CAN_ERROR_NONE 0x00000000U
244#define HAL_CAN_ERROR_EWG 0x00000001U
245#define HAL_CAN_ERROR_EPV 0x00000002U
246#define HAL_CAN_ERROR_BOF 0x00000004U
247#define HAL_CAN_ERROR_STF 0x00000008U
248#define HAL_CAN_ERROR_FOR 0x00000010U
249#define HAL_CAN_ERROR_ACK 0x00000020U
250#define HAL_CAN_ERROR_BR 0x00000040U
251#define HAL_CAN_ERROR_BD 0x00000080U
252#define HAL_CAN_ERROR_CRC 0x00000100U
253#define HAL_CAN_ERROR_FOV0 0x00000200U
254#define HAL_CAN_ERROR_FOV1 0x00000400U
255#define HAL_CAN_ERROR_TXFAIL 0x00000800U
263#define CAN_INITSTATUS_FAILED ((uint8_t)0x00)
264#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01)
272#define CAN_MODE_NORMAL 0x00000000U
273#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM)
274#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM)
275#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))
283#define CAN_SJW_1TQ 0x00000000U
284#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0)
285#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1)
286#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW)
294#define CAN_BS1_1TQ 0x00000000U
295#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0)
296#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1)
297#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
298#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2)
299#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
300#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
301#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
302#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3)
303#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))
304#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))
305#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
306#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))
307#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
308#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
309#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1)
317#define CAN_BS2_1TQ 0x00000000U
318#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0)
319#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1)
320#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))
321#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2)
322#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))
323#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))
324#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2)
332#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00)
333#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01)
341#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00)
342#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01)
350#define CAN_FILTER_FIFO0 ((uint8_t)0x00)
351#define CAN_FILTER_FIFO1 ((uint8_t)0x01)
359#define CAN_ID_STD 0x00000000U
360#define CAN_ID_EXT 0x00000004U
368#define CAN_RTR_DATA 0x00000000U
369#define CAN_RTR_REMOTE 0x00000002U
377#define CAN_FIFO0 ((uint8_t)0x00)
378#define CAN_FIFO1 ((uint8_t)0x01)
392#define CAN_FLAG_RQCP0 0x00000500U
393#define CAN_FLAG_RQCP1 0x00000508U
394#define CAN_FLAG_RQCP2 0x00000510U
395#define CAN_FLAG_TXOK0 0x00000501U
396#define CAN_FLAG_TXOK1 0x00000509U
397#define CAN_FLAG_TXOK2 0x00000511U
398#define CAN_FLAG_TME0 0x0000051AU
399#define CAN_FLAG_TME1 0x0000051BU
400#define CAN_FLAG_TME2 0x0000051CU
403#define CAN_FLAG_FF0 0x00000203U
404#define CAN_FLAG_FOV0 0x00000204U
406#define CAN_FLAG_FF1 0x00000403U
407#define CAN_FLAG_FOV1 0x00000404U
410#define CAN_FLAG_INAK 0x00000100U
411#define CAN_FLAG_SLAK 0x00000101U
412#define CAN_FLAG_ERRI 0x00000102U
413#define CAN_FLAG_WKU 0x00000103U
414#define CAN_FLAG_SLAKI 0x00000104U
420#define CAN_FLAG_EWG 0x00000300U
421#define CAN_FLAG_EPV 0x00000301U
422#define CAN_FLAG_BOF 0x00000302U
430#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE)
433#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0)
434#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0)
435#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0)
436#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1)
437#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1)
438#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1)
441#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE)
442#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE)
445#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE)
446#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE)
447#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE)
448#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE)
449#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE)
457#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
458#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
459#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
477#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
485#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
493#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
501#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
502((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
531#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
532((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
533 (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
534 (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
535 (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
536 ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
562#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
563((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
564 (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
565 (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
566 (((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))))
577#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
585#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
586(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
587 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
588 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
596#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
597((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
605#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
606(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
607 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
608 ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
619#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
620((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
698#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04)
699#define CAN_FLAG_MASK 0x000000FFU
708#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
709 ((MODE) == CAN_MODE_LOOPBACK)|| \
710 ((MODE) == CAN_MODE_SILENT) || \
711 ((MODE) == CAN_MODE_SILENT_LOOPBACK))
712#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
713 ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
714#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
715#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
716#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
717#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
718#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
719 ((MODE) == CAN_FILTERMODE_IDLIST))
720#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
721 ((SCALE) == CAN_FILTERSCALE_32BIT))
722#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
723 ((FIFO) == CAN_FILTER_FIFO1))
724#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
726#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
727#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU))
728#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
729#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
731#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
732 ((IDTYPE) == CAN_ID_EXT))
733#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
734#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
Deinitializes the CAN peripheral registers to their default reset values.
void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
DeInitializes the CAN MSP.
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterConfTypeDef *sFilterConfig)
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)
Initializes the CAN MSP.
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan)
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
Error CAN callback.
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout)
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
Handles CAN interrupt request.
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout)
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
Wake up from sleep mode. When returning with HAL_OK status from this function, Sleep mode is exited.
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
HAL_CAN_StateTypeDef
HAL State structures definition.
@ HAL_CAN_STATE_BUSY_TX_RX0
@ HAL_CAN_STATE_BUSY_RX0_RX1
@ HAL_CAN_STATE_BUSY_TX_RX0_RX1
@ HAL_CAN_STATE_BUSY_TX_RX1
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition
HAL_LockTypeDef
HAL Lock structures definition
CAN filter configuration structure definition.
uint32_t FilterFIFOAssignment
uint32_t FilterMaskIdHigh
uint32_t FilterActivation
CAN handle Structure definition.
CanRxMsgTypeDef * pRx1Msg
__IO HAL_CAN_StateTypeDef State
CAN init structure definition.
CAN Rx message structure definition.
CAN Tx message structure definition.