STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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stm32f4xx_hal_dfsdm.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef __STM32F4xx_HAL_DFSDM_H
21#define __STM32F4xx_HAL_DFSDM_H
22
23#ifdef __cplusplus
24 extern "C" {
25#endif
26
27#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
28/* Includes ------------------------------------------------------------------*/
29#include "stm32f4xx_hal_def.h"
30
39/* Exported types ------------------------------------------------------------*/
47typedef enum
48{
49 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U,
50 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U,
51 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU
52}HAL_DFSDM_Channel_StateTypeDef;
53
57typedef struct
58{
59 FunctionalState Activation;
60 uint32_t Selection;
62 uint32_t Divider;
64}DFSDM_Channel_OutputClockTypeDef;
65
69typedef struct
70{
71 uint32_t Multiplexer;
73 uint32_t DataPacking;
75 uint32_t Pins;
77}DFSDM_Channel_InputTypeDef;
78
82typedef struct
83{
84 uint32_t Type;
86 uint32_t SpiClock;
88}DFSDM_Channel_SerialInterfaceTypeDef;
89
93typedef struct
94{
95 uint32_t FilterOrder;
97 uint32_t Oversampling;
99}DFSDM_Channel_AwdTypeDef;
100
104typedef struct
105{
106 DFSDM_Channel_OutputClockTypeDef OutputClock;
107 DFSDM_Channel_InputTypeDef Input;
108 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface;
109 DFSDM_Channel_AwdTypeDef Awd;
110 int32_t Offset;
112 uint32_t RightBitShift;
114}DFSDM_Channel_InitTypeDef;
115
119#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
120typedef struct __DFSDM_Channel_HandleTypeDef
121#else
122typedef struct
123#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
124{
125 DFSDM_Channel_TypeDef *Instance;
126 DFSDM_Channel_InitTypeDef Init;
127 HAL_DFSDM_Channel_StateTypeDef State;
128#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
129 void (*CkabCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
130 void (*ScdCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
131 void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
132 void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
133#endif
134}DFSDM_Channel_HandleTypeDef;
135
136#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
140typedef enum
141{
142 HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U,
143 HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U,
144 HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U,
145 HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U
146}HAL_DFSDM_Channel_CallbackIDTypeDef;
147
151typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
152#endif
156typedef enum
157{
158 HAL_DFSDM_FILTER_STATE_RESET = 0x00U,
159 HAL_DFSDM_FILTER_STATE_READY = 0x01U,
160 HAL_DFSDM_FILTER_STATE_REG = 0x02U,
161 HAL_DFSDM_FILTER_STATE_INJ = 0x03U,
162 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U,
163 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU
164}HAL_DFSDM_Filter_StateTypeDef;
165
169typedef struct
170{
171 uint32_t Trigger;
173 FunctionalState FastMode;
174 FunctionalState DmaMode;
175}DFSDM_Filter_RegularParamTypeDef;
176
180typedef struct
181{
182 uint32_t Trigger;
184 FunctionalState ScanMode;
185 FunctionalState DmaMode;
186 uint32_t ExtTrigger;
188 uint32_t ExtTriggerEdge;
190}DFSDM_Filter_InjectedParamTypeDef;
191
195typedef struct
196{
197 uint32_t SincOrder;
199 uint32_t Oversampling;
201 uint32_t IntOversampling;
203}DFSDM_Filter_FilterParamTypeDef;
204
208typedef struct
209{
210 DFSDM_Filter_RegularParamTypeDef RegularParam;
211 DFSDM_Filter_InjectedParamTypeDef InjectedParam;
212 DFSDM_Filter_FilterParamTypeDef FilterParam;
213}DFSDM_Filter_InitTypeDef;
214
218#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
219typedef struct __DFSDM_Filter_HandleTypeDef
220#else
221typedef struct
222#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
223{
224 DFSDM_Filter_TypeDef *Instance;
225 DFSDM_Filter_InitTypeDef Init;
226 DMA_HandleTypeDef *hdmaReg;
227 DMA_HandleTypeDef *hdmaInj;
228 uint32_t RegularContMode;
229 uint32_t RegularTrigger;
230 uint32_t InjectedTrigger;
231 uint32_t ExtTriggerEdge;
232 FunctionalState InjectedScanMode;
233 uint32_t InjectedChannelsNbr;
234 uint32_t InjConvRemaining;
235 HAL_DFSDM_Filter_StateTypeDef State;
236 uint32_t ErrorCode;
237#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
238 void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
239 uint32_t Channel, uint32_t Threshold);
240 void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
241 void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
242 void (*InjConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
243 void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
244 void (*ErrorCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
245 void (*MspInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
246 void (*MspDeInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
247#endif
248}DFSDM_Filter_HandleTypeDef;
249
253typedef struct
254{
255 uint32_t DataSource;
257 uint32_t Channel;
259 int32_t HighThreshold;
261 int32_t LowThreshold;
263 uint32_t HighBreakSignal;
265 uint32_t LowBreakSignal;
267}DFSDM_Filter_AwdParamTypeDef;
268
269#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
273typedef enum
274{
275 HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U,
276 HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U,
277 HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U,
278 HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U,
279 HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U,
280 HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U,
281 HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U
282}HAL_DFSDM_Filter_CallbackIDTypeDef;
283
287typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
288typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
289#endif
290
294#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
298typedef struct
299{
300 uint32_t DFSDM1ClockIn;
302 uint32_t DFSDM2ClockIn;
304 uint32_t DFSDM1ClockOut;
306 uint32_t DFSDM2ClockOut;
308 uint32_t DFSDM1BitClkDistribution;
312 uint32_t DFSDM2BitClkDistribution;
318 uint32_t DFSDM1DataDistribution;
320 uint32_t DFSDM2DataDistribution;
322}DFSDM_MultiChannelConfigTypeDef;
323#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
328/* End of exported types -----------------------------------------------------*/
329
330/* Exported constants --------------------------------------------------------*/
338#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U
339#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC
347#define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U
348#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1
356#define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U
357#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0
358#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1
366#define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U
367#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL
375#define DFSDM_CHANNEL_SPI_RISING 0x00000000U
376#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0
377#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1
378#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP
386#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U
387#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0
388#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1
389#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL
397#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U
398#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0
399#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1
400#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD
408#define DFSDM_FILTER_SW_TRIGGER 0x00000000U
409#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U
410#define DFSDM_FILTER_EXT_TRIGGER 0x00000002U
418#if defined(STM32F413xx) || defined(STM32F423xx)
419/* Trigger for stm32f413xx and STM32f423xx devices */
420#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U
421#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0
422#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1
423#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
424#define DFSDM_FILTER_EXT_TRIG_TIM2_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
425#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2
426#define DFSDM_FILTER_EXT_TRIG_TIM11_OC1 DFSDM_FLTCR1_JEXTSEL_2
427#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
428#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
429#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2)
430#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL
431#else
432/* Trigger for stm32f412xx devices */
433#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U
434#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0
435#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1
436#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)
437#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2
438#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)
439#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2)
440#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL
441#endif
449#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0
450#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1
451#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN
459#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U
460#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0
461#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1
462#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)
463#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2
464#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)
472#define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U
473#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL
481#define DFSDM_FILTER_ERROR_NONE 0x00000000U
482#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U
483#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U
484#define DFSDM_FILTER_ERROR_DMA 0x00000003U
485#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
486#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U
487#endif
495#define DFSDM_NO_BREAK_SIGNAL 0x00000000U
496#define DFSDM_BREAK_SIGNAL_0 0x00000001U
497#define DFSDM_BREAK_SIGNAL_1 0x00000002U
498#define DFSDM_BREAK_SIGNAL_2 0x00000004U
499#define DFSDM_BREAK_SIGNAL_3 0x00000008U
507/* DFSDM Channels ------------------------------------------------------------*/
508/* The DFSDM channels are defined as follows:
509 - in 16-bit LSB the channel mask is set
510 - in 16-bit MSB the channel number is set
511 e.g. for channel 3 definition:
512 - the channel mask is 0x00000008 (bit 3 is set)
513 - the channel number 3 is 0x00030000
514 --> Consequently, channel 3 definition is 0x00000008 | 0x00030000 = 0x00030008 */
515#define DFSDM_CHANNEL_0 0x00000001U
516#define DFSDM_CHANNEL_1 0x00010002U
517#define DFSDM_CHANNEL_2 0x00020004U
518#define DFSDM_CHANNEL_3 0x00030008U
519#define DFSDM_CHANNEL_4 0x00040010U /* only for stmm32f413xx and stm32f423xx devices */
520#define DFSDM_CHANNEL_5 0x00050020U /* only for stmm32f413xx and stm32f423xx devices */
521#define DFSDM_CHANNEL_6 0x00060040U /* only for stmm32f413xx and stm32f423xx devices */
522#define DFSDM_CHANNEL_7 0x00070080U /* only for stmm32f413xx and stm32f423xx devices */
530#define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U
531#define DFSDM_CONTINUOUS_CONV_ON 0x00000001U
539#define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U
540#define DFSDM_AWD_LOW_THRESHOLD 0x00000001U
545#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
549#define DFSDM1_CKOUT_DFSDM2_CKOUT 0x00000080U
550#define DFSDM1_CKOUT_DFSDM1 0x00000000U
558#define DFSDM2_CKOUT_DFSDM2_CKOUT 0x00040000U
559#define DFSDM2_CKOUT_DFSDM2 0x00000000U
567#define DFSDM1_CKIN_DFSDM2_CKOUT 0x00000040U
568#define DFSDM1_CKIN_PAD 0x00000000U
576#define DFSDM2_CKIN_DFSDM2_CKOUT 0x00020000U
577#define DFSDM2_CKIN_PAD 0x00000000U
585#define DFSDM1_T4_OC2_BITSTREAM_CKIN0 0x00000000U /* TIM4_OC2 to CLKIN0 */
586#define DFSDM1_T4_OC2_BITSTREAM_CKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL /* TIM4_OC2 to CLKIN2 */
587#define DFSDM1_T4_OC1_BITSTREAM_CKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL /* TIM4_OC1 to CLKIN3 */
588#define DFSDM1_T4_OC1_BITSTREAM_CKIN1 0x00000000U /* TIM4_OC1 to CLKIN1 */
596#define DFSDM2_T3_OC4_BITSTREAM_CKIN0 0x00000000U /* TIM3_OC4 to CKIN0 */
597#define DFSDM2_T3_OC4_BITSTREAM_CKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */
598#define DFSDM2_T3_OC3_BITSTREAM_CKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */
599#define DFSDM2_T3_OC3_BITSTREAM_CKIN1 0x00000000U /* TIM3_OC3 to CKIN1 */
600#define DFSDM2_T3_OC2_BITSTREAM_CKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL /* TIM3_OC2to CKIN6 */
601#define DFSDM2_T3_OC2_BITSTREAM_CKIN2 0x00000000U /* TIM3_OC2 to CKIN2 */
602#define DFSDM2_T3_OC1_BITSTREAM_CKIN3 0x00000000U /* TIM3_OC1 to CKIN3 */
603#define DFSDM2_T3_OC1_BITSTREAM_CKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL /* TIM3_OC1 to CKIN7 */
611#define DFSDM1_DATIN0_TO_DATIN0_PAD 0x00000000U
612#define DFSDM1_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM1D0SEL
613#define DFSDM1_DATIN2_TO_DATIN2_PAD 0x00000000U
614#define DFSDM1_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM1D2SEL
622#define DFSDM2_DATIN0_TO_DATIN0_PAD 0x00000000U
623#define DFSDM2_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM2D0SEL
624#define DFSDM2_DATIN2_TO_DATIN2_PAD 0x00000000U
625#define DFSDM2_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM2D2SEL
626#define DFSDM2_DATIN4_TO_DATIN4_PAD 0x00000000U
627#define DFSDM2_DATIN4_TO_DATIN5_PAD SYSCFG_MCHDLYCR_DFSDM2D4SEL
628#define DFSDM2_DATIN6_TO_DATIN6_PAD 0x00000000U
629#define DFSDM2_DATIN6_TO_DATIN7_PAD SYSCFG_MCHDLYCR_DFSDM2D6SEL
637#define HAL_MCHDLY_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_MCHDLY2EN
638#define HAL_MCHDLY_CLOCK_DFSDM1 SYSCFG_MCHDLYCR_MCHDLY1EN
646#define HAL_DFSDM2_CKIN_PAD 0x00040000U
647#define HAL_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
648#define HAL_DFSDM1_CKIN_PAD 0x00000000U
649#define HAL_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
657#define HAL_DFSDM2_CKOUT_DFSDM2 0x10000000U
658#define HAL_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
659#define HAL_DFSDM1_CKOUT_DFSDM1 0x00000000U
660#define HAL_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
668#define HAL_DATAIN0_DFSDM2_PAD 0x10000000U
669#define HAL_DATAIN0_DFSDM2_DATAIN1 SYSCFG_MCHDLYCR_DFSDM2D0SEL
670#define HAL_DATAIN0_DFSDM1_PAD 0x00000000U
671#define HAL_DATAIN0_DFSDM1_DATAIN1 SYSCFG_MCHDLYCR_DFSDM1D0SEL
679#define HAL_DATAIN2_DFSDM2_PAD 0x10000000U
680#define HAL_DATAIN2_DFSDM2_DATAIN3 SYSCFG_MCHDLYCR_DFSDM2D2SEL
681#define HAL_DATAIN2_DFSDM1_PAD 0x00000000U
682#define HAL_DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL
690#define HAL_DATAIN4_DFSDM2_PAD 0x00000000U
691#define HAL_DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL
699#define HAL_DATAIN6_DFSDM2_PAD 0x00000000U
700#define HAL_DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL
708#define HAL_DFSDM1_CLKIN0_TIM4OC2 0x01000000U
709#define HAL_DFSDM1_CLKIN2_TIM4OC2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
710#define HAL_DFSDM1_CLKIN1_TIM4OC1 0x02000000U
711#define HAL_DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
719#define HAL_DFSDM2_CLKIN0_TIM3OC4 0x04000000U
720#define HAL_DFSDM2_CLKIN4_TIM3OC4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
721#define HAL_DFSDM2_CLKIN1_TIM3OC3 0x08000000U
722#define HAL_DFSDM2_CLKIN5_TIM3OC3 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
723#define HAL_DFSDM2_CLKIN2_TIM3OC2 0x10000000U
724#define HAL_DFSDM2_CLKIN6_TIM3OC2 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
725#define HAL_DFSDM2_CLKIN3_TIM3OC1 0x00000000U
726#define HAL_DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
731#endif /* SYSCFG_MCHDLYCR_BSCKSEL*/
735/* End of exported constants -------------------------------------------------*/
736
737/* Exported macros -----------------------------------------------------------*/
746#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
747#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \
748 (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \
749 (__HANDLE__)->MspInitCallback = NULL; \
750 (__HANDLE__)->MspDeInitCallback = NULL; \
751 } while(0)
752#else
753#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
754#endif
755
760#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
761#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \
762 (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \
763 (__HANDLE__)->MspInitCallback = NULL; \
764 (__HANDLE__)->MspDeInitCallback = NULL; \
765 } while(0)
766#else
767#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
768#endif
769
773/* End of exported macros ----------------------------------------------------*/
774
775/* Exported functions --------------------------------------------------------*/
783/* Channel initialization and de-initialization functions *********************/
784HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
785HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
786void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
787void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
788#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
789/* Channel callbacks register/unregister functions ****************************/
790HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
791 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
792 pDFSDM_Channel_CallbackTypeDef pCallback);
793HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
794 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);
795#endif
803/* Channel operation functions ************************************************/
804HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
805HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
806HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
807HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
808
809HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
810HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
811HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
812HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
813
814int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
815HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
816
817HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
818HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
819
820void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
821void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
829/* Channel state function *****************************************************/
830HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
838/* Filter initialization and de-initialization functions *********************/
839HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
840HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
841void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
842void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
843#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
844/* Filter callbacks register/unregister functions ****************************/
845HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
846 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
847 pDFSDM_Filter_CallbackTypeDef pCallback);
848HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
849 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);
850HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
851 pDFSDM_Filter_AwdCallbackTypeDef pCallback);
852HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
853#endif
861/* Filter control functions *********************/
862HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
863 uint32_t Channel,
864 uint32_t ContinuousMode);
865HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
866 uint32_t Channel);
874/* Filter operation functions *********************/
875HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
876HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
877HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
878HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
879HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
880HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
881HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
882HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
883HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
884HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
885HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
886HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
887HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
888HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
889HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
890 const DFSDM_Filter_AwdParamTypeDef* awdParam);
891HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
892HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
893HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
894
895int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
896int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
897int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
898int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
899uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
900
901void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
902
903HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
904HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
905
906void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
907void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
908void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
909void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
910void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
911void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
919/* Filter state functions *****************************************************/
920HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
921uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
928#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
929void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct);
930void HAL_DFSDM_BitstreamClock_Start(void);
931void HAL_DFSDM_BitstreamClock_Stop(void);
932void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY);
933void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY);
934void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source);
935void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source);
936void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source);
937void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source);
938void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source);
939void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source);
940void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source);
941#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
948/* End of exported functions -------------------------------------------------*/
949
950/* Private macros ------------------------------------------------------------*/
954#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
955 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
956#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
957#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
958 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
959#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
960 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
961 ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
962#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
963 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
964#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
965 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
966 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
967 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
968#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
969 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
970 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
971 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
972#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
973 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
974 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
975 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
976#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U))
977#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
978#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU)
979#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU)
980#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
981 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
982#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
983 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
984 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
985#if defined (STM32F413xx) || defined (STM32F423xx)
986#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
987 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
988 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
989 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
990 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM2_TRGO) || \
991 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
992 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM11_OC1) || \
993 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
994 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
995 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
996#define IS_DFSDM_DELAY_CLOCK(CLOCK) (((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM2) || \
997 ((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1))
998#else
999#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
1000 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
1001 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
1002 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
1003 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
1004 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
1005 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
1006 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
1007#endif
1008#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
1009 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
1010 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
1011#define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
1012 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
1013 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
1014 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
1015 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
1016 ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
1017#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U))
1018#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U))
1019#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
1020 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
1021#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
1022#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0x0FU)
1023#if defined(DFSDM2_Channel0)
1024#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
1025 ((CHANNEL) == DFSDM_CHANNEL_1) || \
1026 ((CHANNEL) == DFSDM_CHANNEL_2) || \
1027 ((CHANNEL) == DFSDM_CHANNEL_3) || \
1028 ((CHANNEL) == DFSDM_CHANNEL_4) || \
1029 ((CHANNEL) == DFSDM_CHANNEL_5) || \
1030 ((CHANNEL) == DFSDM_CHANNEL_6) || \
1031 ((CHANNEL) == DFSDM_CHANNEL_7))
1032#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))
1033#else
1034#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
1035 ((CHANNEL) == DFSDM_CHANNEL_1) || \
1036 ((CHANNEL) == DFSDM_CHANNEL_2) || \
1037 ((CHANNEL) == DFSDM_CHANNEL_3))
1038#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))
1039#endif
1040#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
1041 ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
1042#if defined(DFSDM2_Channel0)
1043#define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
1044 ((INSTANCE) == DFSDM1_Channel1) || \
1045 ((INSTANCE) == DFSDM1_Channel2) || \
1046 ((INSTANCE) == DFSDM1_Channel3))
1047#define IS_DFSDM1_FILTER_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
1048 ((INSTANCE) == DFSDM1_Filter1))
1049#endif /* DFSDM2_Channel0 */
1050
1051#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
1052#define IS_DFSDM_CLOCKIN_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKIN_PAD) || \
1053 ((SELECTION) == HAL_DFSDM2_CKIN_DM) || \
1054 ((SELECTION) == HAL_DFSDM1_CKIN_PAD) || \
1055 ((SELECTION) == HAL_DFSDM1_CKIN_DM))
1056#define IS_DFSDM_CLOCKOUT_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKOUT_DFSDM2) || \
1057 ((SELECTION) == HAL_DFSDM2_CKOUT_M27) || \
1058 ((SELECTION) == HAL_DFSDM1_CKOUT_DFSDM1) || \
1059 ((SELECTION) == HAL_DFSDM1_CKOUT_M27))
1060#define IS_DFSDM_DATAIN0_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN0_DFSDM2_PAD) || \
1061 ((SELECTION) == HAL_DATAIN0_DFSDM2_DATAIN1) || \
1062 ((SELECTION) == HAL_DATAIN0_DFSDM1_PAD) || \
1063 ((SELECTION) == HAL_DATAIN0_DFSDM1_DATAIN1))
1064#define IS_DFSDM_DATAIN2_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN2_DFSDM2_PAD) || \
1065 ((SELECTION) == HAL_DATAIN2_DFSDM2_DATAIN3) || \
1066 ((SELECTION) == HAL_DATAIN2_DFSDM1_PAD) || \
1067 ((SELECTION) == HAL_DATAIN2_DFSDM1_DATAIN3))
1068#define IS_DFSDM_DATAIN4_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN4_DFSDM2_PAD) || \
1069 ((SELECTION) == HAL_DATAIN4_DFSDM2_DATAIN5))
1070#define IS_DFSDM_DATAIN6_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN6_DFSDM2_PAD) || \
1071 ((SELECTION) == HAL_DATAIN6_DFSDM2_DATAIN7))
1072#define IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(DISTRIBUTION) (((DISTRIBUTION) == HAL_DFSDM1_CLKIN0_TIM4OC2) || \
1073 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN2_TIM4OC2) || \
1074 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN1_TIM4OC1) || \
1075 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN3_TIM4OC1) || \
1076 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN0_TIM3OC4) || \
1077 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN4_TIM3OC4) || \
1078 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN1_TIM3OC3)|| \
1079 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN5_TIM3OC3) || \
1080 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN2_TIM3OC2) || \
1081 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN6_TIM3OC2) || \
1082 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN3_TIM3OC1)|| \
1083 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN7_TIM3OC1))
1084#define IS_DFSDM_DFSDM1_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM1_CKOUT_DFSDM2_CKOUT) || \
1085 ((CLKOUT) == DFSDM1_CKOUT_DFSDM1))
1086#define IS_DFSDM_DFSDM2_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM2_CKOUT_DFSDM2_CKOUT) || \
1087 ((CLKOUT) == DFSDM2_CKOUT_DFSDM2))
1088#define IS_DFSDM_DFSDM1_CLKIN(CLKIN) (((CLKIN) == DFSDM1_CKIN_DFSDM2_CKOUT) || \
1089 ((CLKIN) == DFSDM1_CKIN_PAD))
1090#define IS_DFSDM_DFSDM2_CLKIN(CLKIN) (((CLKIN) == DFSDM2_CKIN_DFSDM2_CKOUT) || \
1091 ((CLKIN) == DFSDM2_CKIN_PAD))
1092#define IS_DFSDM_DFSDM1_BIT_CLK(CLK) (((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN0) || \
1093 ((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN2) || \
1094 ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN3) || \
1095 ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN1) || \
1096 ((CLK) <= 0x30U))
1097
1098#define IS_DFSDM_DFSDM2_BIT_CLK(CLK) (((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN0) || \
1099 ((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN4) || \
1100 ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN5) || \
1101 ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN1) || \
1102 ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN6) || \
1103 ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN2) || \
1104 ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN3) || \
1105 ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN7)|| \
1106 ((CLK) <= 0x1E000U))
1107
1108#define IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN0_PAD )|| \
1109 ((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN1_PAD) || \
1110 ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN2_PAD) || \
1111 ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN3_PAD)|| \
1112 ((DISTRIBUTION) <= 0xCU))
1113
1114#define IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN0_PAD)|| \
1115 ((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN1_PAD)|| \
1116 ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN2_PAD)|| \
1117 ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN3_PAD)|| \
1118 ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN4_PAD)|| \
1119 ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN5_PAD)|| \
1120 ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN6_PAD)|| \
1121 ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN7_PAD)|| \
1122 ((DISTRIBUTION) <= 0x1D00U))
1123#endif /* (SYSCFG_MCHDLYCR_BSCKSEL) */
1127/* End of private macros -----------------------------------------------------*/
1128
1136#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
1137#ifdef __cplusplus
1138}
1139#endif
1140
1141#endif /* __STM32F4xx_HAL_DFSDM_H */
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition stm32f4xx_hal_def.h:39
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition stm32f4xx_hal_dma.h:139