halDoc/stm32f4xx__hal__dsi_8h_source.html

/* Define to prevent recursive inclusion -------------------------------------*/

#ifndef STM32F4xx_HAL_DSI_H

#define STM32F4xx_HAL_DSI_H


#ifdef __cplusplus

extern "C" {

#endif


/* Includes ------------------------------------------------------------------*/

#include "stm32f4xx_hal_def.h"


#if defined(DSI)


/* Exported types ------------------------------------------------------------*/


typedef struct

{

  uint32_t AutomaticClockLaneControl;

  uint32_t TXEscapeCkdiv;

  uint32_t NumberOfLanes;

} DSI_InitTypeDef;


typedef struct

{

  uint32_t PLLNDIV;

  uint32_t PLLIDF;

  uint32_t PLLODF;

} DSI_PLLInitTypeDef;


typedef struct

{

  uint32_t VirtualChannelID;

  uint32_t ColorCoding;

  uint32_t LooselyPacked;

  uint32_t Mode;

  uint32_t PacketSize;

  uint32_t NumberOfChunks;

  uint32_t NullPacketSize;

  uint32_t HSPolarity;

  uint32_t VSPolarity;

  uint32_t DEPolarity;

  uint32_t HorizontalSyncActive;

  uint32_t HorizontalBackPorch;

  uint32_t HorizontalLine;

  uint32_t VerticalSyncActive;

  uint32_t VerticalBackPorch;

  uint32_t VerticalFrontPorch;

  uint32_t VerticalActive;

  uint32_t LPCommandEnable;

  uint32_t LPLargestPacketSize;

  uint32_t LPVACTLargestPacketSize;

  uint32_t LPHorizontalFrontPorchEnable;

  uint32_t LPHorizontalBackPorchEnable;

  uint32_t LPVerticalActiveEnable;

  uint32_t LPVerticalFrontPorchEnable;

  uint32_t LPVerticalBackPorchEnable;

  uint32_t LPVerticalSyncActiveEnable;

  uint32_t FrameBTAAcknowledgeEnable;

} DSI_VidCfgTypeDef;


typedef struct

{

  uint32_t VirtualChannelID;

  uint32_t ColorCoding;

  uint32_t CommandSize;

  uint32_t TearingEffectSource;

  uint32_t TearingEffectPolarity;

  uint32_t HSPolarity;

  uint32_t VSPolarity;

  uint32_t DEPolarity;

  uint32_t VSyncPol;

  uint32_t AutomaticRefresh;

  uint32_t TEAcknowledgeRequest;

} DSI_CmdCfgTypeDef;


typedef struct

{

  uint32_t LPGenShortWriteNoP;

  uint32_t LPGenShortWriteOneP;

  uint32_t LPGenShortWriteTwoP;

  uint32_t LPGenShortReadNoP;

  uint32_t LPGenShortReadOneP;

  uint32_t LPGenShortReadTwoP;

  uint32_t LPGenLongWrite;

  uint32_t LPDcsShortWriteNoP;

  uint32_t LPDcsShortWriteOneP;

  uint32_t LPDcsShortReadNoP;

  uint32_t LPDcsLongWrite;

  uint32_t LPMaxReadPacket;

  uint32_t AcknowledgeRequest;

} DSI_LPCmdTypeDef;


typedef struct

{

  uint32_t ClockLaneHS2LPTime;

  uint32_t ClockLaneLP2HSTime;

  uint32_t DataLaneHS2LPTime;

  uint32_t DataLaneLP2HSTime;

  uint32_t DataLaneMaxReadTime;

  uint32_t StopWaitTime;

} DSI_PHY_TimerTypeDef;


typedef struct

{

  uint32_t TimeoutCkdiv;

  uint32_t HighSpeedTransmissionTimeout;

  uint32_t LowPowerReceptionTimeout;

  uint32_t HighSpeedReadTimeout;

  uint32_t LowPowerReadTimeout;

  uint32_t HighSpeedWriteTimeout;

  uint32_t HighSpeedWritePrespMode;

  uint32_t LowPowerWriteTimeout;

  uint32_t BTATimeout;

} DSI_HOST_TimeoutTypeDef;


typedef enum

{

  HAL_DSI_STATE_RESET   = 0x00U,

  HAL_DSI_STATE_READY   = 0x01U,

  HAL_DSI_STATE_ERROR   = 0x02U,

  HAL_DSI_STATE_BUSY    = 0x03U,

  HAL_DSI_STATE_TIMEOUT = 0x04U

} HAL_DSI_StateTypeDef;


#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)

typedef struct __DSI_HandleTypeDef

#else


typedef struct

#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */

{

  DSI_TypeDef               *Instance;

  DSI_InitTypeDef           Init;

  HAL_LockTypeDef           Lock;

  __IO HAL_DSI_StateTypeDef State;

  __IO uint32_t             ErrorCode;

  uint32_t                  ErrorMsk;

#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)

  void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi);

  void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi);

  void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi);

  void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi);

  void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi);

#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */


} DSI_HandleTypeDef;


#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)

typedef enum

{

  HAL_DSI_MSPINIT_CB_ID            = 0x00U,

  HAL_DSI_MSPDEINIT_CB_ID          = 0x01U,

  HAL_DSI_TEARING_EFFECT_CB_ID     = 0x02U,

  HAL_DSI_ENDOF_REFRESH_CB_ID      = 0x03U,

  HAL_DSI_ERROR_CB_ID              = 0x04U

} HAL_DSI_CallbackIDTypeDef;


typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);

#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */

/* Exported constants --------------------------------------------------------*/

#define DSI_ENTER_IDLE_MODE       0x39U

#define DSI_ENTER_INVERT_MODE     0x21U

#define DSI_ENTER_NORMAL_MODE     0x13U

#define DSI_ENTER_PARTIAL_MODE    0x12U

#define DSI_ENTER_SLEEP_MODE      0x10U

#define DSI_EXIT_IDLE_MODE        0x38U

#define DSI_EXIT_INVERT_MODE      0x20U

#define DSI_EXIT_SLEEP_MODE       0x11U

#define DSI_GET_3D_CONTROL        0x3FU

#define DSI_GET_ADDRESS_MODE      0x0BU

#define DSI_GET_BLUE_CHANNEL      0x08U

#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU

#define DSI_GET_DISPLAY_MODE      0x0DU

#define DSI_GET_GREEN_CHANNEL     0x07U

#define DSI_GET_PIXEL_FORMAT      0x0CU

#define DSI_GET_POWER_MODE        0x0AU

#define DSI_GET_RED_CHANNEL       0x06U

#define DSI_GET_SCANLINE          0x45U

#define DSI_GET_SIGNAL_MODE       0x0EU

#define DSI_NOP                   0x00U

#define DSI_READ_DDB_CONTINUE     0xA8U

#define DSI_READ_DDB_START        0xA1U

#define DSI_READ_MEMORY_CONTINUE  0x3EU

#define DSI_READ_MEMORY_START     0x2EU

#define DSI_SET_3D_CONTROL        0x3DU

#define DSI_SET_ADDRESS_MODE      0x36U

#define DSI_SET_COLUMN_ADDRESS    0x2AU

#define DSI_SET_DISPLAY_OFF       0x28U

#define DSI_SET_DISPLAY_ON        0x29U

#define DSI_SET_GAMMA_CURVE       0x26U

#define DSI_SET_PAGE_ADDRESS      0x2BU

#define DSI_SET_PARTIAL_COLUMNS   0x31U

#define DSI_SET_PARTIAL_ROWS      0x30U

#define DSI_SET_PIXEL_FORMAT      0x3AU

#define DSI_SET_SCROLL_AREA       0x33U

#define DSI_SET_SCROLL_START      0x37U

#define DSI_SET_TEAR_OFF          0x34U

#define DSI_SET_TEAR_ON           0x35U

#define DSI_SET_TEAR_SCANLINE     0x44U

#define DSI_SET_VSYNC_TIMING      0x40U

#define DSI_SOFT_RESET            0x01U

#define DSI_WRITE_LUT             0x2DU

#define DSI_WRITE_MEMORY_CONTINUE 0x3CU

#define DSI_WRITE_MEMORY_START    0x2CU

#define DSI_VID_MODE_NB_PULSES    0U

#define DSI_VID_MODE_NB_EVENTS    1U

#define DSI_VID_MODE_BURST        2U

#define DSI_COLOR_MODE_FULL       0x00000000U

#define DSI_COLOR_MODE_EIGHT      DSI_WCR_COLM

#define DSI_DISPLAY_ON            0x00000000U

#define DSI_DISPLAY_OFF           DSI_WCR_SHTDN

#define DSI_LP_COMMAND_DISABLE    0x00000000U

#define DSI_LP_COMMAND_ENABLE     DSI_VMCR_LPCE

#define DSI_LP_HFP_DISABLE        0x00000000U

#define DSI_LP_HFP_ENABLE         DSI_VMCR_LPHFPE

#define DSI_LP_HBP_DISABLE        0x00000000U

#define DSI_LP_HBP_ENABLE         DSI_VMCR_LPHBPE

#define DSI_LP_VACT_DISABLE       0x00000000U

#define DSI_LP_VACT_ENABLE        DSI_VMCR_LPVAE

#define DSI_LP_VFP_DISABLE       0x00000000U

#define DSI_LP_VFP_ENABLE        DSI_VMCR_LPVFPE

#define DSI_LP_VBP_DISABLE       0x00000000U

#define DSI_LP_VBP_ENABLE        DSI_VMCR_LPVBPE

#define DSI_LP_VSYNC_DISABLE     0x00000000U

#define DSI_LP_VSYNC_ENABLE      DSI_VMCR_LPVSAE

#define DSI_FBTAA_DISABLE        0x00000000U

#define DSI_FBTAA_ENABLE         DSI_VMCR_FBTAAE

#define DSI_TE_DSILINK           0x00000000U

#define DSI_TE_EXTERNAL          DSI_WCFGR_TESRC

#define DSI_TE_RISING_EDGE       0x00000000U

#define DSI_TE_FALLING_EDGE      DSI_WCFGR_TEPOL

#define DSI_VSYNC_FALLING        0x00000000U

#define DSI_VSYNC_RISING         DSI_WCFGR_VSPOL

#define DSI_AR_DISABLE           0x00000000U

#define DSI_AR_ENABLE            DSI_WCFGR_AR

#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U

#define DSI_TE_ACKNOWLEDGE_ENABLE  DSI_CMCR_TEARE

#define DSI_ACKNOWLEDGE_DISABLE   0x00000000U

#define DSI_ACKNOWLEDGE_ENABLE    DSI_CMCR_ARE

#define DSI_LP_GSW0P_DISABLE     0x00000000U

#define DSI_LP_GSW0P_ENABLE      DSI_CMCR_GSW0TX

#define DSI_LP_GSW1P_DISABLE     0x00000000U

#define DSI_LP_GSW1P_ENABLE      DSI_CMCR_GSW1TX

#define DSI_LP_GSW2P_DISABLE     0x00000000U

#define DSI_LP_GSW2P_ENABLE      DSI_CMCR_GSW2TX

#define DSI_LP_GSR0P_DISABLE     0x00000000U

#define DSI_LP_GSR0P_ENABLE      DSI_CMCR_GSR0TX

#define DSI_LP_GSR1P_DISABLE     0x00000000U

#define DSI_LP_GSR1P_ENABLE      DSI_CMCR_GSR1TX

#define DSI_LP_GSR2P_DISABLE     0x00000000U

#define DSI_LP_GSR2P_ENABLE      DSI_CMCR_GSR2TX

#define DSI_LP_GLW_DISABLE       0x00000000U

#define DSI_LP_GLW_ENABLE        DSI_CMCR_GLWTX

#define DSI_LP_DSW0P_DISABLE     0x00000000U

#define DSI_LP_DSW0P_ENABLE      DSI_CMCR_DSW0TX

#define DSI_LP_DSW1P_DISABLE     0x00000000U

#define DSI_LP_DSW1P_ENABLE      DSI_CMCR_DSW1TX

#define DSI_LP_DSR0P_DISABLE     0x00000000U

#define DSI_LP_DSR0P_ENABLE      DSI_CMCR_DSR0TX

#define DSI_LP_DLW_DISABLE       0x00000000U

#define DSI_LP_DLW_ENABLE        DSI_CMCR_DLWTX

#define DSI_LP_MRDP_DISABLE      0x00000000U

#define DSI_LP_MRDP_ENABLE       DSI_CMCR_MRDPS

#define DSI_HS_PM_DISABLE        0x00000000U

#define DSI_HS_PM_ENABLE         DSI_TCCR3_PM

#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U

#define DSI_AUTO_CLK_LANE_CTRL_ENABLE  DSI_CLCR_ACR

#define DSI_ONE_DATA_LANE          0U

#define DSI_TWO_DATA_LANES         1U

#define DSI_FLOW_CONTROL_CRC_RX    DSI_PCR_CRCRXE

#define DSI_FLOW_CONTROL_ECC_RX    DSI_PCR_ECCRXE

#define DSI_FLOW_CONTROL_BTA       DSI_PCR_BTAE

#define DSI_FLOW_CONTROL_EOTP_RX   DSI_PCR_ETRXE

#define DSI_FLOW_CONTROL_EOTP_TX   DSI_PCR_ETTXE


#define DSI_FLOW_CONTROL_ALL       (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX  | \

                                    DSI_FLOW_CONTROL_BTA    | DSI_FLOW_CONTROL_EOTP_RX | \

                                    DSI_FLOW_CONTROL_EOTP_TX)


#define DSI_RGB565                 0x00000000U

#define DSI_RGB666                 0x00000003U

#define DSI_RGB888                 0x00000005U

#define DSI_LOOSELY_PACKED_ENABLE  DSI_LCOLCR_LPE

#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U

#define DSI_HSYNC_ACTIVE_HIGH       0x00000000U

#define DSI_HSYNC_ACTIVE_LOW        DSI_LPCR_HSP

#define DSI_VSYNC_ACTIVE_HIGH       0x00000000U

#define DSI_VSYNC_ACTIVE_LOW        DSI_LPCR_VSP

#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U

#define DSI_DATA_ENABLE_ACTIVE_LOW  DSI_LPCR_DEP

#define DSI_PLL_IN_DIV1             0x00000001U

#define DSI_PLL_IN_DIV2             0x00000002U

#define DSI_PLL_IN_DIV3             0x00000003U

#define DSI_PLL_IN_DIV4             0x00000004U

#define DSI_PLL_IN_DIV5             0x00000005U

#define DSI_PLL_IN_DIV6             0x00000006U

#define DSI_PLL_IN_DIV7             0x00000007U

#define DSI_PLL_OUT_DIV1            0x00000000U

#define DSI_PLL_OUT_DIV2            0x00000001U

#define DSI_PLL_OUT_DIV4            0x00000002U

#define DSI_PLL_OUT_DIV8            0x00000003U

#define DSI_FLAG_TE                 DSI_WISR_TEIF

#define DSI_FLAG_ER                 DSI_WISR_ERIF

#define DSI_FLAG_BUSY               DSI_WISR_BUSY

#define DSI_FLAG_PLLLS              DSI_WISR_PLLLS

#define DSI_FLAG_PLLL               DSI_WISR_PLLLIF

#define DSI_FLAG_PLLU               DSI_WISR_PLLUIF

#define DSI_FLAG_RRS                DSI_WISR_RRS

#define DSI_FLAG_RR                 DSI_WISR_RRIF

#define DSI_IT_TE                   DSI_WIER_TEIE

#define DSI_IT_ER                   DSI_WIER_ERIE

#define DSI_IT_PLLL                 DSI_WIER_PLLLIE

#define DSI_IT_PLLU                 DSI_WIER_PLLUIE

#define DSI_IT_RR                   DSI_WIER_RRIE

#define DSI_DCS_SHORT_PKT_WRITE_P0  0x00000005U

#define DSI_DCS_SHORT_PKT_WRITE_P1  0x00000015U

#define DSI_GEN_SHORT_PKT_WRITE_P0  0x00000003U

#define DSI_GEN_SHORT_PKT_WRITE_P1  0x00000013U

#define DSI_GEN_SHORT_PKT_WRITE_P2  0x00000023U

#define DSI_DCS_LONG_PKT_WRITE      0x00000039U

#define DSI_GEN_LONG_PKT_WRITE      0x00000029U

#define DSI_DCS_SHORT_PKT_READ      0x00000006U

#define DSI_GEN_SHORT_PKT_READ_P0   0x00000004U

#define DSI_GEN_SHORT_PKT_READ_P1   0x00000014U

#define DSI_GEN_SHORT_PKT_READ_P2   0x00000024U

#define HAL_DSI_ERROR_NONE              0U

#define HAL_DSI_ERROR_ACK               0x00000001U

#define HAL_DSI_ERROR_PHY               0x00000002U

#define HAL_DSI_ERROR_TX                0x00000004U

#define HAL_DSI_ERROR_RX                0x00000008U

#define HAL_DSI_ERROR_ECC               0x00000010U

#define HAL_DSI_ERROR_CRC               0x00000020U

#define HAL_DSI_ERROR_PSE               0x00000040U

#define HAL_DSI_ERROR_EOT               0x00000080U

#define HAL_DSI_ERROR_OVF               0x00000100U

#define HAL_DSI_ERROR_GEN               0x00000200U

#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)

#define HAL_DSI_ERROR_INVALID_CALLBACK  0x00000400U

#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */

#define DSI_CLOCK_LANE              0x00000000U

#define DSI_DATA_LANES              0x00000001U

#define DSI_SLEW_RATE_HSTX          0x00000000U

#define DSI_SLEW_RATE_LPTX          0x00000001U

#define DSI_HS_DELAY                0x00000002U

#define DSI_SWAP_LANE_PINS          0x00000000U

#define DSI_INVERT_HS_SIGNAL        0x00000001U

#define DSI_CLK_LANE                0x00000000U

#define DSI_DATA_LANE0              0x00000001U

#define DSI_DATA_LANE1              0x00000002U

#define DSI_TCLK_POST               0x00000000U

#define DSI_TLPX_CLK                0x00000001U

#define DSI_THS_EXIT                0x00000002U

#define DSI_TLPX_DATA               0x00000003U

#define DSI_THS_ZERO                0x00000004U

#define DSI_THS_TRAIL               0x00000005U

#define DSI_THS_PREPARE             0x00000006U

#define DSI_TCLK_ZERO               0x00000007U

#define DSI_TCLK_PREPARE            0x00000008U

/* Exported macros -----------------------------------------------------------*/

#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)

#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{                                               \

                                                     (__HANDLE__)->State = HAL_DSI_STATE_RESET;    \

                                                     (__HANDLE__)->MspInitCallback = NULL;         \

                                                     (__HANDLE__)->MspDeInitCallback = NULL;       \

                                                   } while(0)

#else

#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)

#endif /*USE_HAL_DSI_REGISTER_CALLBACKS */


#define __HAL_DSI_ENABLE(__HANDLE__) do { \

                                          __IO uint32_t tmpreg = 0x00U; \

                                          SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\

                                          /* Delay after an DSI Host enabling */ \

                                          tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\

                                          UNUSED(tmpreg); \

                                        } while(0U)


#define __HAL_DSI_DISABLE(__HANDLE__) do { \

                                           __IO uint32_t tmpreg = 0x00U; \

                                           CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\

                                           /* Delay after an DSI Host disabling */ \

                                           tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\

                                           UNUSED(tmpreg); \

                                         } while(0U)


#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \

                                                  __IO uint32_t tmpreg = 0x00U; \

                                                  SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\

                                                  /* Delay after an DSI wrapper enabling */ \

                                                  tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\

                                                  UNUSED(tmpreg); \

                                                } while(0U)


#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \

                                                   __IO uint32_t tmpreg = 0x00U; \

                                                   CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\

                                                   /* Delay after an DSI wrapper disabling*/ \

                                                   tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\

                                                   UNUSED(tmpreg); \

                                                 } while(0U)


#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \

                                              __IO uint32_t tmpreg = 0x00U; \

                                              SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\

                                              /* Delay after an DSI PLL enabling */ \

                                              tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\

                                              UNUSED(tmpreg); \

                                            } while(0U)


#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \

                                               __IO uint32_t tmpreg = 0x00U; \

                                               CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\

                                               /* Delay after an DSI PLL disabling */ \

                                               tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\

                                               UNUSED(tmpreg); \

                                             } while(0U)


#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \

                                              __IO uint32_t tmpreg = 0x00U; \

                                              SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\

                                              /* Delay after an DSI regulator enabling */ \

                                              tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\

                                              UNUSED(tmpreg); \

                                            } while(0U)


#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \

                                               __IO uint32_t tmpreg = 0x00U; \

                                               CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\

                                               /* Delay after an DSI regulator disabling */ \

                                               tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\

                                               UNUSED(tmpreg); \

                                             } while(0U)


#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))


#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))


#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))


#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))


#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))


/* Exported functions --------------------------------------------------------*/

HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);

HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);

void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);

void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);

HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);

/* Callbacks Register/UnRegister functions  ***********************************/

#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)

HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,

                                           pDSI_CallbackTypeDef pCallback);

HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);

#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */

void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);

void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);

void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);

void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);

HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);

HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);

HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);

HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);

HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);

HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);

HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);

HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);

HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);

HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);

HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);

HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);

HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,

                                     uint32_t ChannelID,

                                     uint32_t Mode,

                                     uint32_t Param1,

                                     uint32_t Param2);

HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,

                                    uint32_t ChannelID,

                                    uint32_t Mode,

                                    uint32_t NbParams,

                                    uint32_t Param1,

                                    const uint8_t *ParametersTable);

HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,

                               uint32_t ChannelNbr,

                               uint8_t *Array,

                               uint32_t Size,

                               uint32_t Mode,

                               uint32_t DCSCmd,

                               uint8_t *ParametersTable);

HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);

HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);

HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);

HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);


HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);

HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);


HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,

                                                    uint32_t Value);

HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);

HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);

HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,

                                                   FunctionalState State);

HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State,

                                        uint32_t Value);

HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);

HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);

HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);

HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);

HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);


uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi);

HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi);


/* Private types -------------------------------------------------------------*/

/* Private defines -----------------------------------------------------------*/

/* Private variables ---------------------------------------------------------*/

/* Private constants ---------------------------------------------------------*/

#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U)

/* Private macros ------------------------------------------------------------*/

#define IS_DSI_PLL_NDIV(NDIV)                       ((10U <= (NDIV)) && ((NDIV) <= 125U))


#define IS_DSI_PLL_IDF(IDF)                         (((IDF) == DSI_PLL_IN_DIV1) || \

                                                     ((IDF) == DSI_PLL_IN_DIV2) || \

                                                     ((IDF) == DSI_PLL_IN_DIV3) || \

                                                     ((IDF) == DSI_PLL_IN_DIV4) || \

                                                     ((IDF) == DSI_PLL_IN_DIV5) || \

                                                     ((IDF) == DSI_PLL_IN_DIV6) || \

                                                     ((IDF) == DSI_PLL_IN_DIV7))


#define IS_DSI_PLL_ODF(ODF)                         (((ODF) == DSI_PLL_OUT_DIV1) || \

                                                     ((ODF) == DSI_PLL_OUT_DIV2) || \

                                                     ((ODF) == DSI_PLL_OUT_DIV4) || \

                                                     ((ODF) == DSI_PLL_OUT_DIV8))


#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane)    (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\

                                                     || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))


#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes)       (((NumberOfLanes) == DSI_ONE_DATA_LANE)\

                                                     || ((NumberOfLanes) == DSI_TWO_DATA_LANES))


#define IS_DSI_FLOW_CONTROL(FlowControl)            (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)

#define IS_DSI_COLOR_CODING(ColorCoding)            ((ColorCoding) <= 5U)


#define IS_DSI_LOOSELY_PACKED(LooselyPacked)        (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\

                                                     || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))


#define IS_DSI_DE_POLARITY(DataEnable)              (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\

                                                     || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))


#define IS_DSI_VSYNC_POLARITY(Vsync)                (((Vsync) == DSI_VSYNC_ACTIVE_HIGH)\

                                                     || ((Vsync) == DSI_VSYNC_ACTIVE_LOW))


#define IS_DSI_HSYNC_POLARITY(Hsync)                (((Hsync) == DSI_HSYNC_ACTIVE_HIGH)\

                                                     || ((Hsync) == DSI_HSYNC_ACTIVE_LOW))


#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType)       (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \

                                                     ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \

                                                     ((VideoModeType) == DSI_VID_MODE_BURST))


#define IS_DSI_COLOR_MODE(ColorMode)                (((ColorMode) == DSI_COLOR_MODE_FULL)\

                                                     || ((ColorMode) == DSI_COLOR_MODE_EIGHT))


#define IS_DSI_SHUT_DOWN(ShutDown)                  (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))


#define IS_DSI_LP_COMMAND(LPCommand)                (((LPCommand) == DSI_LP_COMMAND_DISABLE)\

                                                     || ((LPCommand) == DSI_LP_COMMAND_ENABLE))


#define IS_DSI_LP_HFP(LPHFP)                        (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))

#define IS_DSI_LP_HBP(LPHBP)                        (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))


#define IS_DSI_LP_VACTIVE(LPVActive)                (((LPVActive) == DSI_LP_VACT_DISABLE)\

                                                     || ((LPVActive) == DSI_LP_VACT_ENABLE))


#define IS_DSI_LP_VFP(LPVFP)                        (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))

#define IS_DSI_LP_VBP(LPVBP)                        (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))


#define IS_DSI_LP_VSYNC(LPVSYNC)                    (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\

                                                     || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))


#define IS_DSI_FBTAA(FrameBTAAcknowledge)           (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\

                                                     || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))


#define IS_DSI_TE_SOURCE(TESource)                  (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))


#define IS_DSI_TE_POLARITY(TEPolarity)              (((TEPolarity) == DSI_TE_RISING_EDGE)\

                                                     || ((TEPolarity) == DSI_TE_FALLING_EDGE))


#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh)  (((AutomaticRefresh) == DSI_AR_DISABLE)\

                                                     || ((AutomaticRefresh) == DSI_AR_ENABLE))


#define IS_DSI_VS_POLARITY(VSPolarity)              (((VSPolarity) == DSI_VSYNC_FALLING)\

                                                     || ((VSPolarity) == DSI_VSYNC_RISING))


#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\

                                                     || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))


#define IS_DSI_ACK_REQUEST(AcknowledgeRequest)      (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\

                                                     || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))


#define IS_DSI_LP_GSW0P(LP_GSW0P)                   (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\

                                                     || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))


#define IS_DSI_LP_GSW1P(LP_GSW1P)                   (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\

                                                     || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))


#define IS_DSI_LP_GSW2P(LP_GSW2P)                   (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\

                                                     || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))


#define IS_DSI_LP_GSR0P(LP_GSR0P)                   (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\

                                                     || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))


#define IS_DSI_LP_GSR1P(LP_GSR1P)                   (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\

                                                     || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))


#define IS_DSI_LP_GSR2P(LP_GSR2P)                   (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\

                                                     || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))


#define IS_DSI_LP_GLW(LP_GLW)                       (((LP_GLW) == DSI_LP_GLW_DISABLE)\

                                                     || ((LP_GLW) == DSI_LP_GLW_ENABLE))


#define IS_DSI_LP_DSW0P(LP_DSW0P)                   (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\

                                                     || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))


#define IS_DSI_LP_DSW1P(LP_DSW1P)                   (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\

                                                     || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))


#define IS_DSI_LP_DSR0P(LP_DSR0P)                   (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\

                                                     || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))


#define IS_DSI_LP_DLW(LP_DLW)                       (((LP_DLW) == DSI_LP_DLW_DISABLE)\

                                                     || ((LP_DLW) == DSI_LP_DLW_ENABLE))


#define IS_DSI_LP_MRDP(LP_MRDP)                     (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\

                                                     || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))


#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE)        (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \

                                                     ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \

                                                     ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \

                                                     ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \

                                                     ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))


#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE)         (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \

                                                     ((MODE) == DSI_GEN_LONG_PKT_WRITE))


#define IS_DSI_READ_PACKET_TYPE(MODE)               (((MODE) == DSI_DCS_SHORT_PKT_READ) || \

                                                     ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \

                                                     ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \

                                                     ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))


#define IS_DSI_COMMUNICATION_DELAY(CommDelay)       (((CommDelay) == DSI_SLEW_RATE_HSTX) || \

                                                     ((CommDelay) == DSI_SLEW_RATE_LPTX) || \

                                                     ((CommDelay) == DSI_HS_DELAY))


#define IS_DSI_LANE_GROUP(Lane)                     (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))


#define IS_DSI_CUSTOM_LANE(CustomLane)              (((CustomLane) == DSI_SWAP_LANE_PINS)\

                                                     || ((CustomLane) == DSI_INVERT_HS_SIGNAL))


#define IS_DSI_LANE(Lane)                           (((Lane) == DSI_CLOCK_LANE) || \

                                                     ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))


#define IS_DSI_PHY_TIMING(Timing)                   (((Timing) == DSI_TCLK_POST   ) || \

                                                     ((Timing) == DSI_TLPX_CLK    ) || \

                                                     ((Timing) == DSI_THS_EXIT    ) || \

                                                     ((Timing) == DSI_TLPX_DATA   ) || \

                                                     ((Timing) == DSI_THS_ZERO    ) || \

                                                     ((Timing) == DSI_THS_TRAIL   ) || \

                                                     ((Timing) == DSI_THS_PREPARE ) || \

                                                     ((Timing) == DSI_TCLK_ZERO   ) || \

                                                     ((Timing) == DSI_TCLK_PREPARE))


#endif /* DSI */


#ifdef __cplusplus

}

#endif


#endif /* STM32F4xx_HAL_DSI_H */

HAL_DSI_StateTypeDef
HAL_DSI_StateTypeDef
DSI States Structure definition.
Definition stm32f4xx_hal_dsi.h:294

HAL_DSI_STATE_RESET
@ HAL_DSI_STATE_RESET
Definition stm32f4xx_hal_dsi.h:295

HAL_DSI_STATE_ERROR
@ HAL_DSI_STATE_ERROR
Definition stm32f4xx_hal_dsi.h:297

HAL_DSI_STATE_TIMEOUT
@ HAL_DSI_STATE_TIMEOUT
Definition stm32f4xx_hal_dsi.h:299

HAL_DSI_STATE_READY
@ HAL_DSI_STATE_READY
Definition stm32f4xx_hal_dsi.h:296

HAL_DSI_STATE_BUSY
@ HAL_DSI_STATE_BUSY
Definition stm32f4xx_hal_dsi.h:298

HAL_DSI_Init
HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
Initializes the DSI according to the specified parameters in the DSI_InitTypeDef and create the assoc...
Definition stm32f4xx_hal_dsi.c:309

HAL_DSI_DeInit
HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
De-initializes the DSI peripheral registers to their default reset values.
Definition stm32f4xx_hal_dsi.c:485

HAL_DSI_ConfigErrorMonitor
HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
Enable the error monitor flags.
Definition stm32f4xx_hal_dsi.c:543

HAL_DSI_MspDeInit
void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi)
De-initializes the DSI MSP.
Definition stm32f4xx_hal_dsi.c:641

HAL_DSI_MspInit
void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi)
Initializes the DSI MSP.
Definition stm32f4xx_hal_dsi.c:626

HAL_DSI_IRQHandler
void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
Handles DSI interrupt request.
Definition stm32f4xx_hal_dsi.c:856

HAL_DSI_ErrorCallback
void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
Operation Error DSI callback.
Definition stm32f4xx_hal_dsi.c:1008

HAL_DSI_TearingEffectCallback
void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
Tearing Effect DSI callback.
Definition stm32f4xx_hal_dsi.c:978

HAL_DSI_EndOfRefreshCallback
void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
End of Refresh DSI callback.
Definition stm32f4xx_hal_dsi.c:993

HAL_DSI_ForceRXLowPower
HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
Force LP Receiver in Low-Power Mode.
Definition stm32f4xx_hal_dsi.c:3018

HAL_DSI_ForceDataLanesInRX
HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
Force Data Lanes in RX Mode after a BTA.
Definition stm32f4xx_hal_dsi.c:3043

HAL_DSI_Shutdown
HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
Control the display shutdown in Video mode.
Definition stm32f4xx_hal_dsi.c:1595

HAL_DSI_ShortWrite
HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, uint32_t ChannelID, uint32_t Mode, uint32_t Param1, uint32_t Param2)
write short DCS or short Generic command
Definition stm32f4xx_hal_dsi.c:1626

HAL_DSI_LongWrite
HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t ChannelID, uint32_t Mode, uint32_t NbParams, uint32_t Param1, const uint8_t *ParametersTable)
write long DCS or long Generic command
Definition stm32f4xx_hal_dsi.c:1661

HAL_DSI_EnterULPMData
HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running (only data lanes are in ULPM)
Definition stm32f4xx_hal_dsi.c:1866

HAL_DSI_SetSDD
HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
Activate an additional current path on all lanes to meet the SDDTx parameter defined in the MIPI D-PH...
Definition stm32f4xx_hal_dsi.c:2713

HAL_DSI_ConfigHostTimeouts
HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
Configure the DSI HOST timeout parameters.
Definition stm32f4xx_hal_dsi.c:1448

HAL_DSI_ExitULPMData
HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running (only data lanes are in ULPM)
Definition stm32f4xx_hal_dsi.c:2018

HAL_DSI_EnterULPM
HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off (both data and clock lanes are in...
Definition stm32f4xx_hal_dsi.c:2194

HAL_DSI_SetPHYTimings
HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
Set custom timing for the PHY.
Definition stm32f4xx_hal_dsi.c:2829

HAL_DSI_ConfigVideoMode
HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
Select video mode and configure the corresponding parameters.
Definition stm32f4xx_hal_dsi.c:1091

HAL_DSI_ExitULPM
HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off (both data and clock lanes are in ...
Definition stm32f4xx_hal_dsi.c:2356

HAL_DSI_ConfigPhyTimer
HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
Configure the DSI PHY timer parameters.
Definition stm32f4xx_hal_dsi.c:1401

HAL_DSI_ForceTXStopMode
HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
Force the Clock/Data Lane in TX Stop Mode.
Definition stm32f4xx_hal_dsi.c:2976

HAL_DSI_ConfigCommand
HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
Configure command transmission mode: High-speed or Low-power and enable/disable acknowledge request a...
Definition stm32f4xx_hal_dsi.c:1312

HAL_DSI_SetContentionDetectionOff
HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
Switch off the contention detection on data lanes.
Definition stm32f4xx_hal_dsi.c:3093

HAL_DSI_SetLowPowerRXFilter
HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
Low-Power Reception Filter Tuning.
Definition stm32f4xx_hal_dsi.c:2690

HAL_DSI_PatternGeneratorStart
HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
Start test pattern generation.
Definition stm32f4xx_hal_dsi.c:2549

HAL_DSI_SetSlewRateAndDelayTuning
HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
Set Slew-Rate And Delay Tuning.
Definition stm32f4xx_hal_dsi.c:2598

HAL_DSI_PatternGeneratorStop
HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
Stop test pattern generation.
Definition stm32f4xx_hal_dsi.c:2573

HAL_DSI_SetGenericVCID
HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
Configure the Generic interface read-back Virtual Channel ID.
Definition stm32f4xx_hal_dsi.c:1068

HAL_DSI_Start
HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
Start the DSI module.
Definition stm32f4xx_hal_dsi.c:1501

HAL_DSI_Stop
HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
Stop the DSI module.
Definition stm32f4xx_hal_dsi.c:1524

HAL_DSI_SetLanePinsConfiguration
HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
Custom lane pins configuration.
Definition stm32f4xx_hal_dsi.c:2742

HAL_DSI_Refresh
HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
Refresh the display in command mode.
Definition stm32f4xx_hal_dsi.c:1547

HAL_DSI_ConfigFlowControl
HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
Configure the flow control parameters.
Definition stm32f4xx_hal_dsi.c:1375

HAL_DSI_ConfigAdaptedCommandMode
HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
Select adapted command mode and configure the corresponding parameters.
Definition stm32f4xx_hal_dsi.c:1241

HAL_DSI_SetPullDown
HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
Enable a pull-down on the lanes to prevent from floating states when unused.
Definition stm32f4xx_hal_dsi.c:3068

HAL_DSI_ColorMode
HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
Controls the display color mode in Video mode.
Definition stm32f4xx_hal_dsi.c:1569

HAL_DSI_Read
HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, uint32_t ChannelNbr, uint8_t *Array, uint32_t Size, uint32_t Mode, uint32_t DCSCmd, uint8_t *ParametersTable)
Read command (DCS or generic)
Definition stm32f4xx_hal_dsi.c:1750

HAL_DSI_GetError
uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi)
Return the DSI error code.
Definition stm32f4xx_hal_dsi.c:3148

HAL_DSI_GetState
HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi)
Return the DSI state.
Definition stm32f4xx_hal_dsi.c:3137

stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.

HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition stm32f4xx_hal_def.h:39

HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition stm32f4xx_hal_def.h:50

DSI_CmdCfgTypeDef
DSI Adapted command mode configuration.
Definition stm32f4xx_hal_dsi.h:159

DSI_CmdCfgTypeDef::DEPolarity
uint32_t DEPolarity
Definition stm32f4xx_hal_dsi.h:180

DSI_CmdCfgTypeDef::AutomaticRefresh
uint32_t AutomaticRefresh
Definition stm32f4xx_hal_dsi.h:186

DSI_CmdCfgTypeDef::TearingEffectPolarity
uint32_t TearingEffectPolarity
Definition stm32f4xx_hal_dsi.h:171

DSI_CmdCfgTypeDef::TearingEffectSource
uint32_t TearingEffectSource
Definition stm32f4xx_hal_dsi.h:168

DSI_CmdCfgTypeDef::ColorCoding
uint32_t ColorCoding
Definition stm32f4xx_hal_dsi.h:162

DSI_CmdCfgTypeDef::TEAcknowledgeRequest
uint32_t TEAcknowledgeRequest
Definition stm32f4xx_hal_dsi.h:189

DSI_CmdCfgTypeDef::VSyncPol
uint32_t VSyncPol
Definition stm32f4xx_hal_dsi.h:183

DSI_CmdCfgTypeDef::VirtualChannelID
uint32_t VirtualChannelID
Definition stm32f4xx_hal_dsi.h:160

DSI_CmdCfgTypeDef::HSPolarity
uint32_t HSPolarity
Definition stm32f4xx_hal_dsi.h:174

DSI_CmdCfgTypeDef::CommandSize
uint32_t CommandSize
Definition stm32f4xx_hal_dsi.h:165

DSI_CmdCfgTypeDef::VSPolarity
uint32_t VSPolarity
Definition stm32f4xx_hal_dsi.h:177

DSI_HOST_TimeoutTypeDef
DSI HOST Timeouts definition.
Definition stm32f4xx_hal_dsi.h:268

DSI_HOST_TimeoutTypeDef::LowPowerWriteTimeout
uint32_t LowPowerWriteTimeout
Definition stm32f4xx_hal_dsi.h:284

DSI_HOST_TimeoutTypeDef::HighSpeedReadTimeout
uint32_t HighSpeedReadTimeout
Definition stm32f4xx_hal_dsi.h:275

DSI_HOST_TimeoutTypeDef::HighSpeedWriteTimeout
uint32_t HighSpeedWriteTimeout
Definition stm32f4xx_hal_dsi.h:279

DSI_HOST_TimeoutTypeDef::LowPowerReceptionTimeout
uint32_t LowPowerReceptionTimeout
Definition stm32f4xx_hal_dsi.h:273

DSI_HOST_TimeoutTypeDef::LowPowerReadTimeout
uint32_t LowPowerReadTimeout
Definition stm32f4xx_hal_dsi.h:277

DSI_HOST_TimeoutTypeDef::HighSpeedTransmissionTimeout
uint32_t HighSpeedTransmissionTimeout
Definition stm32f4xx_hal_dsi.h:271

DSI_HOST_TimeoutTypeDef::BTATimeout
uint32_t BTATimeout
Definition stm32f4xx_hal_dsi.h:286

DSI_HOST_TimeoutTypeDef::HighSpeedWritePrespMode
uint32_t HighSpeedWritePrespMode
Definition stm32f4xx_hal_dsi.h:281

DSI_HOST_TimeoutTypeDef::TimeoutCkdiv
uint32_t TimeoutCkdiv
Definition stm32f4xx_hal_dsi.h:269

DSI_HandleTypeDef
DSI Handle Structure definition.
Definition stm32f4xx_hal_dsi.h:310

DSI_HandleTypeDef::State
__IO HAL_DSI_StateTypeDef State
Definition stm32f4xx_hal_dsi.h:314

DSI_HandleTypeDef::Init
DSI_InitTypeDef Init
Definition stm32f4xx_hal_dsi.h:312

DSI_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition stm32f4xx_hal_dsi.h:313

DSI_HandleTypeDef::ErrorMsk
uint32_t ErrorMsk
Definition stm32f4xx_hal_dsi.h:316

DSI_HandleTypeDef::Instance
DSI_TypeDef * Instance
Definition stm32f4xx_hal_dsi.h:311

DSI_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition stm32f4xx_hal_dsi.h:315

DSI_InitTypeDef
DSI Init Structure definition.
Definition stm32f4xx_hal_dsi.h:49

DSI_InitTypeDef::NumberOfLanes
uint32_t NumberOfLanes
Definition stm32f4xx_hal_dsi.h:56

DSI_InitTypeDef::AutomaticClockLaneControl
uint32_t AutomaticClockLaneControl
Definition stm32f4xx_hal_dsi.h:50

DSI_InitTypeDef::TXEscapeCkdiv
uint32_t TXEscapeCkdiv
Definition stm32f4xx_hal_dsi.h:53

DSI_LPCmdTypeDef
DSI command transmission mode configuration.
Definition stm32f4xx_hal_dsi.h:198

DSI_LPCmdTypeDef::LPGenShortReadOneP
uint32_t LPGenShortReadOneP
Definition stm32f4xx_hal_dsi.h:211

DSI_LPCmdTypeDef::LPDcsLongWrite
uint32_t LPDcsLongWrite
Definition stm32f4xx_hal_dsi.h:229

DSI_LPCmdTypeDef::LPGenLongWrite
uint32_t LPGenLongWrite
Definition stm32f4xx_hal_dsi.h:217

DSI_LPCmdTypeDef::LPMaxReadPacket
uint32_t LPMaxReadPacket
Definition stm32f4xx_hal_dsi.h:232

DSI_LPCmdTypeDef::LPDcsShortWriteNoP
uint32_t LPDcsShortWriteNoP
Definition stm32f4xx_hal_dsi.h:220

DSI_LPCmdTypeDef::LPGenShortReadNoP
uint32_t LPGenShortReadNoP
Definition stm32f4xx_hal_dsi.h:208

DSI_LPCmdTypeDef::LPDcsShortWriteOneP
uint32_t LPDcsShortWriteOneP
Definition stm32f4xx_hal_dsi.h:223

DSI_LPCmdTypeDef::LPDcsShortReadNoP
uint32_t LPDcsShortReadNoP
Definition stm32f4xx_hal_dsi.h:226

DSI_LPCmdTypeDef::LPGenShortWriteOneP
uint32_t LPGenShortWriteOneP
Definition stm32f4xx_hal_dsi.h:202

DSI_LPCmdTypeDef::LPGenShortReadTwoP
uint32_t LPGenShortReadTwoP
Definition stm32f4xx_hal_dsi.h:214

DSI_LPCmdTypeDef::AcknowledgeRequest
uint32_t AcknowledgeRequest
Definition stm32f4xx_hal_dsi.h:235

DSI_LPCmdTypeDef::LPGenShortWriteTwoP
uint32_t LPGenShortWriteTwoP
Definition stm32f4xx_hal_dsi.h:205

DSI_LPCmdTypeDef::LPGenShortWriteNoP
uint32_t LPGenShortWriteNoP
Definition stm32f4xx_hal_dsi.h:199

DSI_PHY_TimerTypeDef
DSI PHY Timings definition.
Definition stm32f4xx_hal_dsi.h:244

DSI_PHY_TimerTypeDef::ClockLaneLP2HSTime
uint32_t ClockLaneLP2HSTime
Definition stm32f4xx_hal_dsi.h:248

DSI_PHY_TimerTypeDef::DataLaneMaxReadTime
uint32_t DataLaneMaxReadTime
Definition stm32f4xx_hal_dsi.h:257

DSI_PHY_TimerTypeDef::DataLaneLP2HSTime
uint32_t DataLaneLP2HSTime
Definition stm32f4xx_hal_dsi.h:254

DSI_PHY_TimerTypeDef::DataLaneHS2LPTime
uint32_t DataLaneHS2LPTime
Definition stm32f4xx_hal_dsi.h:251

DSI_PHY_TimerTypeDef::StopWaitTime
uint32_t StopWaitTime
Definition stm32f4xx_hal_dsi.h:259

DSI_PHY_TimerTypeDef::ClockLaneHS2LPTime
uint32_t ClockLaneHS2LPTime
Definition stm32f4xx_hal_dsi.h:245

DSI_PLLInitTypeDef
DSI PLL Clock structure definition.
Definition stm32f4xx_hal_dsi.h:65

DSI_PLLInitTypeDef::PLLODF
uint32_t PLLODF
Definition stm32f4xx_hal_dsi.h:72

DSI_PLLInitTypeDef::PLLIDF
uint32_t PLLIDF
Definition stm32f4xx_hal_dsi.h:69

DSI_PLLInitTypeDef::PLLNDIV
uint32_t PLLNDIV
Definition stm32f4xx_hal_dsi.h:66

DSI_VidCfgTypeDef
DSI Video mode configuration.
Definition stm32f4xx_hal_dsi.h:81

DSI_VidCfgTypeDef::VerticalActive
uint32_t VerticalActive
Definition stm32f4xx_hal_dsi.h:121

DSI_VidCfgTypeDef::LPVerticalBackPorchEnable
uint32_t LPVerticalBackPorchEnable
Definition stm32f4xx_hal_dsi.h:144

DSI_VidCfgTypeDef::VerticalFrontPorch
uint32_t VerticalFrontPorch
Definition stm32f4xx_hal_dsi.h:119

DSI_VidCfgTypeDef::HorizontalSyncActive
uint32_t HorizontalSyncActive
Definition stm32f4xx_hal_dsi.h:109

DSI_VidCfgTypeDef::LPLargestPacketSize
uint32_t LPLargestPacketSize
Definition stm32f4xx_hal_dsi.h:126

DSI_VidCfgTypeDef::VirtualChannelID
uint32_t VirtualChannelID
Definition stm32f4xx_hal_dsi.h:82

DSI_VidCfgTypeDef::LPHorizontalBackPorchEnable
uint32_t LPHorizontalBackPorchEnable
Definition stm32f4xx_hal_dsi.h:135

DSI_VidCfgTypeDef::LPVerticalSyncActiveEnable
uint32_t LPVerticalSyncActiveEnable
Definition stm32f4xx_hal_dsi.h:147

DSI_VidCfgTypeDef::HSPolarity
uint32_t HSPolarity
Definition stm32f4xx_hal_dsi.h:100

DSI_VidCfgTypeDef::NumberOfChunks
uint32_t NumberOfChunks
Definition stm32f4xx_hal_dsi.h:96

DSI_VidCfgTypeDef::FrameBTAAcknowledgeEnable
uint32_t FrameBTAAcknowledgeEnable
Definition stm32f4xx_hal_dsi.h:150

DSI_VidCfgTypeDef::HorizontalLine
uint32_t HorizontalLine
Definition stm32f4xx_hal_dsi.h:113

DSI_VidCfgTypeDef::LPVerticalFrontPorchEnable
uint32_t LPVerticalFrontPorchEnable
Definition stm32f4xx_hal_dsi.h:141

DSI_VidCfgTypeDef::LPVerticalActiveEnable
uint32_t LPVerticalActiveEnable
Definition stm32f4xx_hal_dsi.h:138

DSI_VidCfgTypeDef::VSPolarity
uint32_t VSPolarity
Definition stm32f4xx_hal_dsi.h:103

DSI_VidCfgTypeDef::LPCommandEnable
uint32_t LPCommandEnable
Definition stm32f4xx_hal_dsi.h:123

DSI_VidCfgTypeDef::PacketSize
uint32_t PacketSize
Definition stm32f4xx_hal_dsi.h:94

DSI_VidCfgTypeDef::VerticalSyncActive
uint32_t VerticalSyncActive
Definition stm32f4xx_hal_dsi.h:115

DSI_VidCfgTypeDef::NullPacketSize
uint32_t NullPacketSize
Definition stm32f4xx_hal_dsi.h:98

DSI_VidCfgTypeDef::HorizontalBackPorch
uint32_t HorizontalBackPorch
Definition stm32f4xx_hal_dsi.h:111

DSI_VidCfgTypeDef::VerticalBackPorch
uint32_t VerticalBackPorch
Definition stm32f4xx_hal_dsi.h:117

DSI_VidCfgTypeDef::ColorCoding
uint32_t ColorCoding
Definition stm32f4xx_hal_dsi.h:84

DSI_VidCfgTypeDef::LooselyPacked
uint32_t LooselyPacked
Definition stm32f4xx_hal_dsi.h:87

DSI_VidCfgTypeDef::DEPolarity
uint32_t DEPolarity
Definition stm32f4xx_hal_dsi.h:106

DSI_VidCfgTypeDef::LPVACTLargestPacketSize
uint32_t LPVACTLargestPacketSize
Definition stm32f4xx_hal_dsi.h:129

DSI_VidCfgTypeDef::LPHorizontalFrontPorchEnable
uint32_t LPHorizontalFrontPorchEnable
Definition stm32f4xx_hal_dsi.h:132

DSI_VidCfgTypeDef::Mode
uint32_t Mode
Definition stm32f4xx_hal_dsi.h:91