STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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stm32f4xx_hal_eth_legacy.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef __STM32F4xx_HAL_ETH_LEGACY_H
21#define __STM32F4xx_HAL_ETH_LEGACY_H
22
23#ifdef __cplusplus
24 extern "C" {
25#endif
26
27#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
28 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
29/* Includes ------------------------------------------------------------------*/
30#include "stm32f4xx_hal_def.h"
31
43#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
44#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
45 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
46#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
47 ((SPEED) == ETH_SPEED_100M))
48#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
49 ((MODE) == ETH_MODE_HALFDUPLEX))
50#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
51 ((MODE) == ETH_RXINTERRUPT_MODE))
52#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
53 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
54#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
55 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
56#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
57 ((CMD) == ETH_WATCHDOG_DISABLE))
58#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
59 ((CMD) == ETH_JABBER_DISABLE))
60#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
61 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
62 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
63 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
64 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
65 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
66 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
67 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
68#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
69 ((CMD) == ETH_CARRIERSENCE_DISABLE))
70#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
71 ((CMD) == ETH_RECEIVEOWN_DISABLE))
72#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
73 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
74#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
75 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
76#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
77 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
78#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
79 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
80#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
81 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
82 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
83 ((LIMIT) == ETH_BACKOFFLIMIT_1))
84#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
85 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
86#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
87 ((CMD) == ETH_RECEIVEAll_DISABLE))
88#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
89 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
90 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
91#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
92 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
93 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
94#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
95 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
96#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
97 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
98#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
99 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
100#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
101 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
102 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
103 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
104#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
105 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
106 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
107#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
108#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
109 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
110#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
111 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
112 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
113 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
114#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
115 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
116#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
117 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
118#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
119 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
120#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
121 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
122#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
123#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
124 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
125 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
126 ((ADDRESS) == ETH_MAC_ADDRESS3))
127#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
128 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
129 ((ADDRESS) == ETH_MAC_ADDRESS3))
130#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
131 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
132#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
133 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
134 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
135 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
136 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
137 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
138#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
139 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
140#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
141 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
142#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
143 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
144#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
145 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
146#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
147 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
148 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
149 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
150 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
151 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
152 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
153 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
154#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
155 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
156#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
157 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
158#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
159 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
160 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
161 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
162#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
163 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
164#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
165 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
166#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
167 ((CMD) == ETH_FIXEDBURST_DISABLE))
168#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
169 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
170 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
171 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
172 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
173 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
174 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
175 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
176 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
177 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
178 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
179 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
180#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
181 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
182 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
183 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
184 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
185 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
186 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
187 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
188 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
189 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
190 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
191 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
192#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
193#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
194 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
195 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
196 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
197 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
198#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
199 ((FLAG) == ETH_DMATXDESC_IC) || \
200 ((FLAG) == ETH_DMATXDESC_LS) || \
201 ((FLAG) == ETH_DMATXDESC_FS) || \
202 ((FLAG) == ETH_DMATXDESC_DC) || \
203 ((FLAG) == ETH_DMATXDESC_DP) || \
204 ((FLAG) == ETH_DMATXDESC_TTSE) || \
205 ((FLAG) == ETH_DMATXDESC_TER) || \
206 ((FLAG) == ETH_DMATXDESC_TCH) || \
207 ((FLAG) == ETH_DMATXDESC_TTSS) || \
208 ((FLAG) == ETH_DMATXDESC_IHE) || \
209 ((FLAG) == ETH_DMATXDESC_ES) || \
210 ((FLAG) == ETH_DMATXDESC_JT) || \
211 ((FLAG) == ETH_DMATXDESC_FF) || \
212 ((FLAG) == ETH_DMATXDESC_PCE) || \
213 ((FLAG) == ETH_DMATXDESC_LCA) || \
214 ((FLAG) == ETH_DMATXDESC_NC) || \
215 ((FLAG) == ETH_DMATXDESC_LCO) || \
216 ((FLAG) == ETH_DMATXDESC_EC) || \
217 ((FLAG) == ETH_DMATXDESC_VF) || \
218 ((FLAG) == ETH_DMATXDESC_CC) || \
219 ((FLAG) == ETH_DMATXDESC_ED) || \
220 ((FLAG) == ETH_DMATXDESC_UF) || \
221 ((FLAG) == ETH_DMATXDESC_DB))
222#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
223 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
224#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
225 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
226 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
227 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
228#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
229#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
230 ((FLAG) == ETH_DMARXDESC_AFM) || \
231 ((FLAG) == ETH_DMARXDESC_ES) || \
232 ((FLAG) == ETH_DMARXDESC_DE) || \
233 ((FLAG) == ETH_DMARXDESC_SAF) || \
234 ((FLAG) == ETH_DMARXDESC_LE) || \
235 ((FLAG) == ETH_DMARXDESC_OE) || \
236 ((FLAG) == ETH_DMARXDESC_VLAN) || \
237 ((FLAG) == ETH_DMARXDESC_FS) || \
238 ((FLAG) == ETH_DMARXDESC_LS) || \
239 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
240 ((FLAG) == ETH_DMARXDESC_LC) || \
241 ((FLAG) == ETH_DMARXDESC_FT) || \
242 ((FLAG) == ETH_DMARXDESC_RWT) || \
243 ((FLAG) == ETH_DMARXDESC_RE) || \
244 ((FLAG) == ETH_DMARXDESC_DBE) || \
245 ((FLAG) == ETH_DMARXDESC_CE) || \
246 ((FLAG) == ETH_DMARXDESC_MAMPCE))
247#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
248 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
249#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
250 ((FLAG) == ETH_PMT_FLAG_MPR))
251#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
252#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
253 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
254 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
255 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
256 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
257 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
258 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
259 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
260 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
261 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
262 ((FLAG) == ETH_DMA_FLAG_T))
263#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
264#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
265 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
266 ((IT) == ETH_MAC_IT_PMT))
267#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
268 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
269 ((FLAG) == ETH_MAC_FLAG_PMT))
270#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
271#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
272 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
273 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
274 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
275 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
276 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
277 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
278 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
279 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
280#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
281 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
282#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
283 ((IT) != 0x00U))
284#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
285 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
286 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
287#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
288 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
289
297/* Delay to wait when writing to some Ethernet registers */
298#define ETH_REG_WRITE_DELAY 0x00000001U
299
300/* ETHERNET Errors */
301#define ETH_SUCCESS 0U
302#define ETH_ERROR 1U
303
304/* ETHERNET DMA Tx descriptors Collision Count Shift */
305#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
306
307/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
308#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
309
310/* ETHERNET DMA Rx descriptors Frame Length Shift */
311#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
312
313/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
314#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
315
316/* ETHERNET DMA Rx descriptors Frame length Shift */
317#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
318
319/* ETHERNET MAC address offsets */
320#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
321#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
322
323/* ETHERNET MACMIIAR register Mask */
324#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
325
326/* ETHERNET MACCR register Mask */
327#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
328
329/* ETHERNET MACFCR register Mask */
330#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
331
332/* ETHERNET DMAOMR register Mask */
333#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
334
335/* ETHERNET Remote Wake-up frame register length */
336#define ETH_WAKEUP_REGISTER_LENGTH 8U
337
338/* ETHERNET Missed frames counter Shift */
339#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
344/* Exported types ------------------------------------------------------------*/
352typedef enum
353{
354 HAL_ETH_STATE_RESET = 0x00U,
355 HAL_ETH_STATE_READY = 0x01U,
356 HAL_ETH_STATE_BUSY = 0x02U,
357 HAL_ETH_STATE_BUSY_TX = 0x12U,
358 HAL_ETH_STATE_BUSY_RX = 0x22U,
359 HAL_ETH_STATE_BUSY_TX_RX = 0x32U,
360 HAL_ETH_STATE_BUSY_WR = 0x42U,
361 HAL_ETH_STATE_BUSY_RD = 0x82U,
362 HAL_ETH_STATE_TIMEOUT = 0x03U,
363 HAL_ETH_STATE_ERROR = 0x04U
364}HAL_ETH_StateTypeDef;
365
370typedef struct
371{
372 uint32_t AutoNegotiation;
377 uint32_t Speed;
380 uint32_t DuplexMode;
383 uint16_t PhyAddress;
386 uint8_t *MACAddr;
388 uint32_t RxMode;
391 uint32_t ChecksumMode;
394 uint32_t MediaInterface;
397} ETH_InitTypeDef;
398
399
404typedef struct
405{
406 uint32_t Watchdog;
411 uint32_t Jabber;
416 uint32_t InterFrameGap;
419 uint32_t CarrierSense;
422 uint32_t ReceiveOwn;
427 uint32_t LoopbackMode;
430 uint32_t ChecksumOffload;
433 uint32_t RetryTransmission;
437 uint32_t AutomaticPadCRCStrip;
440 uint32_t BackOffLimit;
443 uint32_t DeferralCheck;
446 uint32_t ReceiveAll;
449 uint32_t SourceAddrFilter;
452 uint32_t PassControlFrames;
455 uint32_t BroadcastFramesReception;
458 uint32_t DestinationAddrFilter;
461 uint32_t PromiscuousMode;
464 uint32_t MulticastFramesFilter;
467 uint32_t UnicastFramesFilter;
470 uint32_t HashTableHigh;
473 uint32_t HashTableLow;
476 uint32_t PauseTime;
479 uint32_t ZeroQuantaPause;
482 uint32_t PauseLowThreshold;
486 uint32_t UnicastPauseFrameDetect;
490 uint32_t ReceiveFlowControl;
494 uint32_t TransmitFlowControl;
498 uint32_t VLANTagComparison;
502 uint32_t VLANTagIdentifier;
504} ETH_MACInitTypeDef;
505
510typedef struct
511{
512 uint32_t DropTCPIPChecksumErrorFrame;
515 uint32_t ReceiveStoreForward;
518 uint32_t FlushReceivedFrame;
521 uint32_t TransmitStoreForward;
524 uint32_t TransmitThresholdControl;
527 uint32_t ForwardErrorFrames;
530 uint32_t ForwardUndersizedGoodFrames;
534 uint32_t ReceiveThresholdControl;
537 uint32_t SecondFrameOperate;
541 uint32_t AddressAlignedBeats;
544 uint32_t FixedBurst;
547 uint32_t RxDMABurstLength;
550 uint32_t TxDMABurstLength;
553 uint32_t EnhancedDescriptorFormat;
556 uint32_t DescriptorSkipLength;
559 uint32_t DMAArbitration;
561} ETH_DMAInitTypeDef;
562
563
568typedef struct
569{
570 __IO uint32_t Status;
572 uint32_t ControlBufferSize;
574 uint32_t Buffer1Addr;
576 uint32_t Buffer2NextDescAddr;
579 uint32_t ExtendedStatus;
581 uint32_t Reserved1;
583 uint32_t TimeStampLow;
585 uint32_t TimeStampHigh;
587} ETH_DMADescTypeDef;
588
592typedef struct
593{
594 ETH_DMADescTypeDef *FSRxDesc;
596 ETH_DMADescTypeDef *LSRxDesc;
598 uint32_t SegCount;
600 uint32_t length;
602 uint32_t buffer;
604} ETH_DMARxFrameInfos;
605
610#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
611typedef struct __ETH_HandleTypeDef
612#else
613typedef struct
614#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
615{
616 ETH_TypeDef *Instance;
618 ETH_InitTypeDef Init;
620 uint32_t LinkStatus;
622 ETH_DMADescTypeDef *RxDesc;
624 ETH_DMADescTypeDef *TxDesc;
626 ETH_DMARxFrameInfos RxFrameInfos;
628 __IO HAL_ETH_StateTypeDef State;
630 HAL_LockTypeDef Lock;
632#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
633
634 void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth);
635 void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth);
636 void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth);
637 void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth);
638 void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth);
640#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
641
642} ETH_HandleTypeDef;
643
644#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
648typedef enum
649{
650 HAL_ETH_MSPINIT_CB_ID = 0x00U,
651 HAL_ETH_MSPDEINIT_CB_ID = 0x01U,
652 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U,
653 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U,
654 HAL_ETH_DMA_ERROR_CB_ID = 0x04U,
656}HAL_ETH_CallbackIDTypeDef;
657
661typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth);
663#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
664
669/* Exported constants --------------------------------------------------------*/
677#define ETH_MAX_PACKET_SIZE 1524U
678#define ETH_HEADER 14U
679#define ETH_CRC 4U
680#define ETH_EXTRA 2U
681#define ETH_VLAN_TAG 4U
682#define ETH_MIN_ETH_PAYLOAD 46U
683#define ETH_MAX_ETH_PAYLOAD 1500U
684#define ETH_JUMBO_FRAME_PAYLOAD 9000U
686 /* Ethernet driver receive buffers are organized in a chained linked-list, when
687 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
688 to the driver receive buffers memory.
689
690 Depending on the size of the received ethernet packet and the size of
691 each ethernet driver receive buffer, the received packet can take one or more
692 ethernet driver receive buffer.
693
694 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
695 and the total count of the driver receive buffers ETH_RXBUFNB.
696
697 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
698 example, they can be reconfigured in the application layer to fit the application
699 needs */
700
701/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
702 packet */
703#ifndef ETH_RX_BUF_SIZE
704 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
705#endif
706
707/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
708#ifndef ETH_RXBUFNB
709 #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
710#endif
711
712
713 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
714 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
715 driver transmit buffers memory to the TxFIFO.
716
717 Depending on the size of the Ethernet packet to be transmitted and the size of
718 each ethernet driver transmit buffer, the packet to be transmitted can take
719 one or more ethernet driver transmit buffer.
720
721 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
722 and the total count of the driver transmit buffers ETH_TXBUFNB.
723
724 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
725 example, they can be reconfigured in the application layer to fit the application
726 needs */
727
728/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
729 packet */
730#ifndef ETH_TX_BUF_SIZE
731 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
732#endif
733
734/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
735#ifndef ETH_TXBUFNB
736 #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
737#endif
738
747/*
748 DMA Tx Descriptor
749 -----------------------------------------------------------------------------------------------
750 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
751 -----------------------------------------------------------------------------------------------
752 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
753 -----------------------------------------------------------------------------------------------
754 TDES2 | Buffer1 Address [31:0] |
755 -----------------------------------------------------------------------------------------------
756 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
757 -----------------------------------------------------------------------------------------------
758*/
759
763#define ETH_DMATXDESC_OWN 0x80000000U
764#define ETH_DMATXDESC_IC 0x40000000U
765#define ETH_DMATXDESC_LS 0x20000000U
766#define ETH_DMATXDESC_FS 0x10000000U
767#define ETH_DMATXDESC_DC 0x08000000U
768#define ETH_DMATXDESC_DP 0x04000000U
769#define ETH_DMATXDESC_TTSE 0x02000000U
770#define ETH_DMATXDESC_CIC 0x00C00000U
771#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U
772#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U
773#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U
774#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U
775#define ETH_DMATXDESC_TER 0x00200000U
776#define ETH_DMATXDESC_TCH 0x00100000U
777#define ETH_DMATXDESC_TTSS 0x00020000U
778#define ETH_DMATXDESC_IHE 0x00010000U
779#define ETH_DMATXDESC_ES 0x00008000U
780#define ETH_DMATXDESC_JT 0x00004000U
781#define ETH_DMATXDESC_FF 0x00002000U
782#define ETH_DMATXDESC_PCE 0x00001000U
783#define ETH_DMATXDESC_LCA 0x00000800U
784#define ETH_DMATXDESC_NC 0x00000400U
785#define ETH_DMATXDESC_LCO 0x00000200U
786#define ETH_DMATXDESC_EC 0x00000100U
787#define ETH_DMATXDESC_VF 0x00000080U
788#define ETH_DMATXDESC_CC 0x00000078U
789#define ETH_DMATXDESC_ED 0x00000004U
790#define ETH_DMATXDESC_UF 0x00000002U
791#define ETH_DMATXDESC_DB 0x00000001U
796#define ETH_DMATXDESC_TBS2 0x1FFF0000U
797#define ETH_DMATXDESC_TBS1 0x00001FFFU
802#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU
807#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU
809 /*---------------------------------------------------------------------------------------------
810 TDES6 | Transmit Time Stamp Low [31:0] |
811 -----------------------------------------------------------------------------------------------
812 TDES7 | Transmit Time Stamp High [31:0] |
813 ----------------------------------------------------------------------------------------------*/
814
815/* Bit definition of TDES6 register */
816 #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */
817
818/* Bit definition of TDES7 register */
819 #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */
820
828/*
829 DMA Rx Descriptor
830 --------------------------------------------------------------------------------------------------------------------
831 RDES0 | OWN(31) | Status [30:0] |
832 ---------------------------------------------------------------------------------------------------------------------
833 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
834 ---------------------------------------------------------------------------------------------------------------------
835 RDES2 | Buffer1 Address [31:0] |
836 ---------------------------------------------------------------------------------------------------------------------
837 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
838 ---------------------------------------------------------------------------------------------------------------------
839*/
840
844#define ETH_DMARXDESC_OWN 0x80000000U
845#define ETH_DMARXDESC_AFM 0x40000000U
846#define ETH_DMARXDESC_FL 0x3FFF0000U
847#define ETH_DMARXDESC_ES 0x00008000U
848#define ETH_DMARXDESC_DE 0x00004000U
849#define ETH_DMARXDESC_SAF 0x00002000U
850#define ETH_DMARXDESC_LE 0x00001000U
851#define ETH_DMARXDESC_OE 0x00000800U
852#define ETH_DMARXDESC_VLAN 0x00000400U
853#define ETH_DMARXDESC_FS 0x00000200U
854#define ETH_DMARXDESC_LS 0x00000100U
855#define ETH_DMARXDESC_IPV4HCE 0x00000080U
856#define ETH_DMARXDESC_LC 0x00000040U
857#define ETH_DMARXDESC_FT 0x00000020U
858#define ETH_DMARXDESC_RWT 0x00000010U
859#define ETH_DMARXDESC_RE 0x00000008U
860#define ETH_DMARXDESC_DBE 0x00000004U
861#define ETH_DMARXDESC_CE 0x00000002U
862#define ETH_DMARXDESC_MAMPCE 0x00000001U
867#define ETH_DMARXDESC_DIC 0x80000000U
868#define ETH_DMARXDESC_RBS2 0x1FFF0000U
869#define ETH_DMARXDESC_RER 0x00008000U
870#define ETH_DMARXDESC_RCH 0x00004000U
871#define ETH_DMARXDESC_RBS1 0x00001FFFU
876#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU
881#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU
883/*---------------------------------------------------------------------------------------------------------------------
884 RDES4 | Reserved[31:15] | Extended Status [14:0] |
885 ---------------------------------------------------------------------------------------------------------------------
886 RDES5 | Reserved[31:0] |
887 ---------------------------------------------------------------------------------------------------------------------
888 RDES6 | Receive Time Stamp Low [31:0] |
889 ---------------------------------------------------------------------------------------------------------------------
890 RDES7 | Receive Time Stamp High [31:0] |
891 --------------------------------------------------------------------------------------------------------------------*/
892
893/* Bit definition of RDES4 register */
894#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */
895#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */
896#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */
897 #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
898 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
899 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
900 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
901 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
902 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
903 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
904#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */
905#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */
906#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */
907#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */
908#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */
909#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */
910 #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
911 #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
912 #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
913
914/* Bit definition of RDES6 register */
915#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */
916
917/* Bit definition of RDES7 register */
918#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */
925#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
926#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
927
934#define ETH_SPEED_10M 0x00000000U
935#define ETH_SPEED_100M 0x00004000U
936
943#define ETH_MODE_FULLDUPLEX 0x00000800U
944#define ETH_MODE_HALFDUPLEX 0x00000000U
951#define ETH_RXPOLLING_MODE 0x00000000U
952#define ETH_RXINTERRUPT_MODE 0x00000001U
960#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
961#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
969#define ETH_MEDIA_INTERFACE_MII 0x00000000U
970#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
978#define ETH_WATCHDOG_ENABLE 0x00000000U
979#define ETH_WATCHDOG_DISABLE 0x00800000U
987#define ETH_JABBER_ENABLE 0x00000000U
988#define ETH_JABBER_DISABLE 0x00400000U
996#define ETH_INTERFRAMEGAP_96BIT 0x00000000U
997#define ETH_INTERFRAMEGAP_88BIT 0x00020000U
998#define ETH_INTERFRAMEGAP_80BIT 0x00040000U
999#define ETH_INTERFRAMEGAP_72BIT 0x00060000U
1000#define ETH_INTERFRAMEGAP_64BIT 0x00080000U
1001#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U
1002#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U
1003#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U
1011#define ETH_CARRIERSENCE_ENABLE 0x00000000U
1012#define ETH_CARRIERSENCE_DISABLE 0x00010000U
1020#define ETH_RECEIVEOWN_ENABLE 0x00000000U
1021#define ETH_RECEIVEOWN_DISABLE 0x00002000U
1029#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
1030#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
1038#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
1039#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
1047#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
1048#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
1056#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
1057#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
1065#define ETH_BACKOFFLIMIT_10 0x00000000U
1066#define ETH_BACKOFFLIMIT_8 0x00000020U
1067#define ETH_BACKOFFLIMIT_4 0x00000040U
1068#define ETH_BACKOFFLIMIT_1 0x00000060U
1076#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
1077#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
1085#define ETH_RECEIVEALL_ENABLE 0x80000000U
1086#define ETH_RECEIVEAll_DISABLE 0x00000000U
1094#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
1095#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
1096#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
1104#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U
1105#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U
1106#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U
1114#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
1115#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
1123#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
1124#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
1132#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
1133#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
1141#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
1142#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
1143#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
1144#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
1152#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
1153#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
1154#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
1162#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
1163#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
1171#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U
1172#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U
1173#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U
1174#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U
1182#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
1183#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
1191#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
1192#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
1200#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
1201#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
1209#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
1210#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
1218#define ETH_MAC_ADDRESS0 0x00000000U
1219#define ETH_MAC_ADDRESS1 0x00000008U
1220#define ETH_MAC_ADDRESS2 0x00000010U
1221#define ETH_MAC_ADDRESS3 0x00000018U
1229#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
1230#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
1238#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U
1239#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U
1240#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U
1241#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U
1242#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U
1243#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U
1251#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
1252#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
1260#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
1261#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
1269#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
1270#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
1278#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
1279#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
1287#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U
1288#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U
1289#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U
1290#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U
1291#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U
1292#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U
1293#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U
1294#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U
1302#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
1303#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
1311#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
1312#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
1320#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U
1321#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U
1322#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U
1323#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U
1331#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
1332#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
1340#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
1341#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
1349#define ETH_FIXEDBURST_ENABLE 0x00010000U
1350#define ETH_FIXEDBURST_DISABLE 0x00000000U
1358#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U
1359#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U
1360#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U
1361#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U
1362#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U
1363#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U
1364#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U
1365#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U
1366#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U
1367#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U
1368#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U
1369#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U
1377#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U
1378#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U
1379#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U
1380#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U
1381#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U
1382#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U
1383#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U
1384#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U
1385#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U
1386#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U
1387#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U
1388#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U
1396#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U
1397#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U
1405#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
1406#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
1407#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
1408#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
1409#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
1417#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U
1418#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U
1426#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U
1427#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U
1428#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U
1429#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U
1437#define ETH_DMARXDESC_BUFFER1 0x00000000U
1438#define ETH_DMARXDESC_BUFFER2 0x00000001U
1446#define ETH_PMT_FLAG_WUFFRPR 0x80000000U
1447#define ETH_PMT_FLAG_WUFR 0x00000040U
1448#define ETH_PMT_FLAG_MPR 0x00000020U
1456#define ETH_MMC_IT_TGF 0x00200000U
1457#define ETH_MMC_IT_TGFMSC 0x00008000U
1458#define ETH_MMC_IT_TGFSC 0x00004000U
1466#define ETH_MMC_IT_RGUF 0x10020000U
1467#define ETH_MMC_IT_RFAE 0x10000040U
1468#define ETH_MMC_IT_RFCE 0x10000020U
1476#define ETH_MAC_FLAG_TST 0x00000200U
1477#define ETH_MAC_FLAG_MMCT 0x00000040U
1478#define ETH_MAC_FLAG_MMCR 0x00000020U
1479#define ETH_MAC_FLAG_MMC 0x00000010U
1480#define ETH_MAC_FLAG_PMT 0x00000008U
1488#define ETH_DMA_FLAG_TST 0x20000000U
1489#define ETH_DMA_FLAG_PMT 0x10000000U
1490#define ETH_DMA_FLAG_MMC 0x08000000U
1491#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U
1492#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U
1493#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U
1494#define ETH_DMA_FLAG_NIS 0x00010000U
1495#define ETH_DMA_FLAG_AIS 0x00008000U
1496#define ETH_DMA_FLAG_ER 0x00004000U
1497#define ETH_DMA_FLAG_FBE 0x00002000U
1498#define ETH_DMA_FLAG_ET 0x00000400U
1499#define ETH_DMA_FLAG_RWT 0x00000200U
1500#define ETH_DMA_FLAG_RPS 0x00000100U
1501#define ETH_DMA_FLAG_RBU 0x00000080U
1502#define ETH_DMA_FLAG_R 0x00000040U
1503#define ETH_DMA_FLAG_TU 0x00000020U
1504#define ETH_DMA_FLAG_RO 0x00000010U
1505#define ETH_DMA_FLAG_TJT 0x00000008U
1506#define ETH_DMA_FLAG_TBU 0x00000004U
1507#define ETH_DMA_FLAG_TPS 0x00000002U
1508#define ETH_DMA_FLAG_T 0x00000001U
1516#define ETH_MAC_IT_TST 0x00000200U
1517#define ETH_MAC_IT_MMCT 0x00000040U
1518#define ETH_MAC_IT_MMCR 0x00000020U
1519#define ETH_MAC_IT_MMC 0x00000010U
1520#define ETH_MAC_IT_PMT 0x00000008U
1528#define ETH_DMA_IT_TST 0x20000000U
1529#define ETH_DMA_IT_PMT 0x10000000U
1530#define ETH_DMA_IT_MMC 0x08000000U
1531#define ETH_DMA_IT_NIS 0x00010000U
1532#define ETH_DMA_IT_AIS 0x00008000U
1533#define ETH_DMA_IT_ER 0x00004000U
1534#define ETH_DMA_IT_FBE 0x00002000U
1535#define ETH_DMA_IT_ET 0x00000400U
1536#define ETH_DMA_IT_RWT 0x00000200U
1537#define ETH_DMA_IT_RPS 0x00000100U
1538#define ETH_DMA_IT_RBU 0x00000080U
1539#define ETH_DMA_IT_R 0x00000040U
1540#define ETH_DMA_IT_TU 0x00000020U
1541#define ETH_DMA_IT_RO 0x00000010U
1542#define ETH_DMA_IT_TJT 0x00000008U
1543#define ETH_DMA_IT_TBU 0x00000004U
1544#define ETH_DMA_IT_TPS 0x00000002U
1545#define ETH_DMA_IT_T 0x00000001U
1553#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U
1554#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U
1555#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U
1556#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U
1557#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U
1558#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U
1568#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U
1569#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U
1570#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U
1571#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U
1572#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U
1573#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U
1582#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U
1583#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U
1591#define ETH_EXTI_LINE_WAKEUP 0x00080000U
1601/* Exported macro ------------------------------------------------------------*/
1611#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1612#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
1613 (__HANDLE__)->State = HAL_ETH_STATE_RESET; \
1614 (__HANDLE__)->MspInitCallback = NULL; \
1615 (__HANDLE__)->MspDeInitCallback = NULL; \
1616 } while(0)
1617#else
1618#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
1619#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
1620
1627#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
1628
1635#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
1636
1642#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
1643
1649#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
1650
1656#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
1657
1663#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
1664
1670#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
1671
1677#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
1678
1684#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
1685
1697#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
1698
1704#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
1705
1711#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
1712
1718#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
1719
1725#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
1726
1737#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
1738
1749#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
1750
1756#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1757
1763#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
1764
1770#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1771
1777#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
1778
1791#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
1792
1800#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
1801
1809#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
1810
1817#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
1818
1825#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
1826
1833#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
1834
1844#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
1845
1852#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
1853
1860#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
1861
1868#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
1869
1875#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
1876
1882#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1883
1889#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
1890
1896#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1897
1903#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
1904
1910#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
1911
1922#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
1923
1929#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
1930
1936#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
1937 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
1938
1944#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
1945
1951#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
1952
1958#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
1959
1965#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
1966
1972#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
1973
1979#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
1980
1986#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
1987
1998#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
2009#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
2020#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
2021
2032#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
2033
2038#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
2039
2044#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
2045
2050#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
2051
2056#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
2057
2062#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
2063
2068#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
2069
2074#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
2075
2080#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2081
2086#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
2087
2092#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2093
2098#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
2099 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
2100 }while(0U)
2101
2106#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2107 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2108 }while(0U)
2109
2114#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
2115
2119/* Exported functions --------------------------------------------------------*/
2120
2125/* Initialization and de-initialization functions ****************************/
2126
2130HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
2131HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
2132void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
2133void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
2134HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
2135HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
2136/* Callbacks Register/UnRegister functions ***********************************/
2137#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
2138HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
2139HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
2140#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
2141
2145/* IO operation functions ****************************************************/
2146
2150HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
2151HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
2152/* Communication with PHY functions*/
2153HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
2154HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
2155/* Non-Blocking mode: Interrupt */
2156HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
2157void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
2158/* Callback in non blocking modes (Interrupt) */
2159void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
2160void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
2161void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
2166/* Peripheral Control functions **********************************************/
2167
2172HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
2173HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
2174HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
2175HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
2180/* Peripheral State functions ************************************************/
2181
2185HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
2202#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
2203 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
2204
2205#ifdef __cplusplus
2206}
2207#endif
2208
2209#endif /* __STM32F4xx_HAL_ETH_LEGACY_H */
HAL_ETH_MspDeInit
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
DeInitializes ETH MSP.
Definition stm32f4xx_hal_eth.c:481
HAL_ETH_MspInit
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
Initializes the ETH MSP.
Definition stm32f4xx_hal_eth.c:466
HAL_ETH_Init
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
Initialize the Ethernet peripheral registers.
Definition stm32f4xx_hal_eth.c:336
HAL_ETH_DeInit
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
DeInitializes the ETH peripheral.
Definition stm32f4xx_hal_eth.c:433
HAL_ETH_Start
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
Enables Ethernet MAC and DMA reception and transmission.
Definition stm32f4xx_hal_eth.c:708
HAL_ETH_WritePHYRegister
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
Writes to a PHY register.
Definition stm32f4xx_hal_eth.c:2132
HAL_ETH_ReadPHYRegister
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
Read a PHY register.
Definition stm32f4xx_hal_eth.c:2081
HAL_ETH_RxCpltCallback
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
Rx Transfer completed callbacks.
Definition stm32f4xx_hal_eth.c:2017
HAL_ETH_TxCpltCallback
void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
Tx Transfer completed callbacks.
Definition stm32f4xx_hal_eth.c:2002
HAL_ETH_ErrorCallback
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
Ethernet transfer error callbacks.
Definition stm32f4xx_hal_eth.c:2032
HAL_ETH_IRQHandler
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
This function handles ETH interrupt request.
Definition stm32f4xx_hal_eth.c:1890
HAL_ETH_Stop
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
Stop Ethernet MAC and DMA reception/transmission.
Definition stm32f4xx_hal_eth.c:833
HAL_ETH_GetState
HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth)
Returns the ETH state.
Definition stm32f4xx_hal_eth.c:2668
HAL_ETH_StateTypeDef
uint32_t HAL_ETH_StateTypeDef
HAL State structures definition.
Definition stm32f4xx_hal_eth.h:480
HAL_ETH_STATE_RESET
#define HAL_ETH_STATE_RESET
Definition stm32f4xx_hal_eth.h:1178
HAL_ETH_STATE_BUSY
#define HAL_ETH_STATE_BUSY
Definition stm32f4xx_hal_eth.h:1180
HAL_ETH_STATE_READY
#define HAL_ETH_STATE_READY
Definition stm32f4xx_hal_eth.h:1179
HAL_ETH_STATE_ERROR
#define HAL_ETH_STATE_ERROR
Definition stm32f4xx_hal_eth.h:1182
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition stm32f4xx_hal_def.h:39
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition stm32f4xx_hal_def.h:50
ETH_DMADescTypeDef
ETH DMA Descriptor structure definition.
Definition stm32f4xx_hal_eth.h:59
ETH_HandleTypeDef
ETH Handle Structure definition.
Definition stm32f4xx_hal_eth.h:527
ETH_InitTypeDef
ETH Init Structure definition.
Definition stm32f4xx_hal_eth.h:428