halDoc/stm32f4xx__hal__eth_8h_source.html

/* Define to prevent recursive inclusion -------------------------------------*/

#ifndef STM32F4xx_HAL_ETH_H

#define STM32F4xx_HAL_ETH_H


#ifdef __cplusplus

extern "C" {

#endif


/* Includes ------------------------------------------------------------------*/

#include "stm32f4xx_hal_def.h"


#if defined(ETH)


/* Exported types ------------------------------------------------------------*/

#ifndef ETH_TX_DESC_CNT

#define ETH_TX_DESC_CNT         4U

#endif /* ETH_TX_DESC_CNT */


#ifndef ETH_RX_DESC_CNT

#define ETH_RX_DESC_CNT         4U

#endif /* ETH_RX_DESC_CNT */


/*********************** Descriptors struct def section ************************/


typedef struct

{

  __IO uint32_t DESC0;

  __IO uint32_t DESC1;

  __IO uint32_t DESC2;

  __IO uint32_t DESC3;

  __IO uint32_t DESC4;

  __IO uint32_t DESC5;

  __IO uint32_t DESC6;

  __IO uint32_t DESC7;

  uint32_t BackupAddr0; /* used to store rx buffer 1 address */

  uint32_t BackupAddr1; /* used to store rx buffer 2 address */

} ETH_DMADescTypeDef;


typedef struct __ETH_BufferTypeDef

{

  uint8_t *buffer;                /*<! buffer address */


  uint32_t len;                   /*<! buffer length */


  struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */

} ETH_BufferTypeDef;


typedef struct

{

  uint32_t  TxDesc[ETH_TX_DESC_CNT];        /*<! Tx DMA descriptors addresses */


  uint32_t  CurTxDesc;                      /*<! Current Tx descriptor index for packet transmission */


  uint32_t *PacketAddress[ETH_TX_DESC_CNT];  /*<! Ethernet packet addresses array */


  uint32_t *CurrentPacketAddress;           /*<! Current transmit NX_PACKET addresses */


  uint32_t BuffersInUse;                   /*<! Buffers in Use */


  uint32_t releaseIndex;                  /*<! Release index */

} ETH_TxDescListTypeDef;


typedef struct

{

  uint32_t Attributes;

  uint32_t Length;

  ETH_BufferTypeDef *TxBuffer;

  uint32_t SrcAddrCtrl;

  uint32_t CRCPadCtrl;

  uint32_t ChecksumCtrl;

  uint32_t MaxSegmentSize;

  uint32_t PayloadLen;

  uint32_t TCPHeaderLen;

  uint32_t VlanTag;

  uint32_t VlanCtrl;

  uint32_t InnerVlanTag;

  uint32_t InnerVlanCtrl;

  void *pData;

} ETH_TxPacketConfigTypeDef;


typedef struct

{

  uint32_t TimeStampLow;

  uint32_t TimeStampHigh;


} ETH_TimeStampTypeDef;


#ifdef HAL_ETH_USE_PTP

typedef struct

{

  uint32_t Seconds;

  uint32_t NanoSeconds;

} ETH_TimeTypeDef;

#endif  /* HAL_ETH_USE_PTP */


typedef struct

{

  uint32_t RxDesc[ETH_RX_DESC_CNT];     /*<! Rx DMA descriptors addresses. */


  uint32_t ItMode;                      /*<! If 1, DMA will generate the Rx complete interrupt.

                                             If 0, DMA will not generate the Rx complete interrupt. */


  uint32_t RxDescIdx;                 /*<! Current Rx descriptor. */


  uint32_t RxDescCnt;                 /*<! Number of descriptors . */


  uint32_t RxDataLength;              /*<! Received Data Length. */


  uint32_t RxBuildDescIdx;            /*<! Current Rx Descriptor for building descriptors. */


  uint32_t RxBuildDescCnt;            /*<! Number of Rx Descriptors awaiting building. */


  uint32_t pRxLastRxDesc;             /*<! Last received descriptor. */


  ETH_TimeStampTypeDef TimeStamp;     /*<! Time Stamp Low value for receive. */


  void *pRxStart;                     /*<! Pointer to the first buff. */


  void *pRxEnd;                       /*<! Pointer to the last buff. */


} ETH_RxDescListTypeDef;


typedef struct

{

  uint32_t

  SourceAddrControl;

  FunctionalState

  ChecksumOffload;

  uint32_t         InterPacketGapVal;

  FunctionalState  GiantPacketSizeLimitControl;

  FunctionalState  Support2KPacket;

  FunctionalState  CRCStripTypePacket;

  FunctionalState  AutomaticPadCRCStrip;

  FunctionalState  Watchdog;

  FunctionalState  Jabber;

  FunctionalState  JumboPacket;

  uint32_t         Speed;

  uint32_t         DuplexMode;

  FunctionalState  LoopbackMode;

  FunctionalState

  CarrierSenseBeforeTransmit;

  FunctionalState  ReceiveOwn;

  FunctionalState

  CarrierSenseDuringTransmit;

  FunctionalState

  RetryTransmission;

  uint32_t         BackOffLimit;

  FunctionalState

  DeferralCheck;

  uint32_t

  PreambleLength;

  FunctionalState  SlowProtocolDetect;

  FunctionalState  CRCCheckingRxPackets;

  uint32_t

  GiantPacketSizeLimit;

  FunctionalState  ExtendedInterPacketGap;

  uint32_t         ExtendedInterPacketGapVal;

  FunctionalState  ProgrammableWatchdog;

  uint32_t         WatchdogTimeout;

  uint32_t

  PauseTime;

  FunctionalState

  ZeroQuantaPause;

  uint32_t

  PauseLowThreshold;

  FunctionalState

  TransmitFlowControl;

  FunctionalState

  UnicastPausePacketDetect;

  FunctionalState  ReceiveFlowControl;

  uint32_t         TransmitQueueMode;

  uint32_t         ReceiveQueueMode;

  FunctionalState  DropTCPIPChecksumErrorPacket;

  FunctionalState  ForwardRxErrorPacket;

  FunctionalState  ForwardRxUndersizedGoodPacket;

} ETH_MACConfigTypeDef;


typedef struct

{

  uint32_t        DMAArbitration;

  FunctionalState AddressAlignedBeats;

  uint32_t        BurstMode;

  FunctionalState      DropTCPIPChecksumErrorFrame;

  FunctionalState      ReceiveStoreForward;

  FunctionalState      TransmitStoreForward;

  uint32_t

  TxDMABurstLength;

  uint32_t             TransmitThresholdControl;

  uint32_t

  RxDMABurstLength;

  FunctionalState      ForwardErrorFrames;

  FunctionalState FlushRxPacket;

  FunctionalState

  ForwardUndersizedGoodFrames;

  uint32_t             ReceiveThresholdControl;

  FunctionalState

  SecondFrameOperate;

  FunctionalState      EnhancedDescriptorFormat;

  uint32_t

  DescriptorSkipLength;

} ETH_DMAConfigTypeDef;


typedef enum

{

  HAL_ETH_MII_MODE             = 0x00U,

  HAL_ETH_RMII_MODE            = SYSCFG_PMC_MII_RMII_SEL

} ETH_MediaInterfaceTypeDef;


#ifdef HAL_ETH_USE_PTP

typedef enum

{

  HAL_ETH_PTP_POSITIVE_UPDATE   = 0x00000000U,

  HAL_ETH_PTP_NEGATIVE_UPDATE   = 0x00000001U

} ETH_PtpUpdateTypeDef;

#endif  /* HAL_ETH_USE_PTP */


typedef struct

{

  uint8_t

  *MACAddr;

  ETH_MediaInterfaceTypeDef   MediaInterface;

  ETH_DMADescTypeDef

  *TxDesc;

  ETH_DMADescTypeDef

  *RxDesc;

  uint32_t                    RxBuffLen;

} ETH_InitTypeDef;


#ifdef HAL_ETH_USE_PTP

typedef struct

{

  uint32_t                    Timestamp;

  uint32_t                    TimestampUpdateMode;

  uint32_t                    TimestampInitialize;

  uint32_t                    TimestampUpdate;

  uint32_t                    TimestampAddendUpdate;

  uint32_t                    TimestampAll;

  uint32_t                    TimestampRolloverMode;

  uint32_t                    TimestampV2;

  uint32_t                    TimestampEthernet;

  uint32_t                    TimestampIPv6;

  uint32_t                    TimestampIPv4;

  uint32_t                    TimestampEvent;

  uint32_t                    TimestampMaster;

  uint32_t                    TimestampFilter;

  uint32_t                    TimestampClockType;

  uint32_t                    TimestampAddend;

  uint32_t                    TimestampSubsecondInc;

} ETH_PTP_ConfigTypeDef;

#endif  /* HAL_ETH_USE_PTP */


typedef uint32_t HAL_ETH_StateTypeDef;

typedef  void (*pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer);

typedef  void (*pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff,

                                            uint16_t Length);

typedef  void (*pETH_txFreeCallbackTypeDef)(uint32_t *buffer);

typedef  void (*pETH_txPtpCallbackTypeDef)(uint32_t *buffer,

                                           ETH_TimeStampTypeDef *timestamp);

#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

typedef struct __ETH_HandleTypeDef

#else


typedef struct

#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */

{

  ETH_TypeDef                *Instance;

  ETH_InitTypeDef            Init;

  ETH_TxDescListTypeDef      TxDescList;

  ETH_RxDescListTypeDef      RxDescList;

#ifdef HAL_ETH_USE_PTP

  ETH_TimeStampTypeDef       TxTimestamp;

#endif /* HAL_ETH_USE_PTP */


  __IO HAL_ETH_StateTypeDef  gState;

  __IO uint32_t              ErrorCode;

  __IO uint32_t

  DMAErrorCode;

  __IO uint32_t

  MACErrorCode;

  __IO uint32_t              MACWakeUpEvent;

  __IO uint32_t              MACLPIEvent;

  __IO uint32_t              IsPtpConfigured;

#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)


  void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth);

  void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth);

  void (* ErrorCallback)(struct __ETH_HandleTypeDef *heth);

  void (* PMTCallback)(struct __ETH_HandleTypeDef *heth);

  void (* WakeUpCallback)(struct __ETH_HandleTypeDef *heth);

  void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth);

  void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth);

#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */


  pETH_rxAllocateCallbackTypeDef  rxAllocateCallback;

  pETH_rxLinkCallbackTypeDef      rxLinkCallback;

  pETH_txFreeCallbackTypeDef      txFreeCallback;

  pETH_txPtpCallbackTypeDef       txPtpCallback;

} ETH_HandleTypeDef;


#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

typedef enum

{

  HAL_ETH_MSPINIT_CB_ID            = 0x00U,

  HAL_ETH_MSPDEINIT_CB_ID          = 0x01U,

  HAL_ETH_TX_COMPLETE_CB_ID        = 0x02U,

  HAL_ETH_RX_COMPLETE_CB_ID        = 0x03U,

  HAL_ETH_ERROR_CB_ID              = 0x04U,

  HAL_ETH_PMT_CB_ID                = 0x06U,

  HAL_ETH_WAKEUP_CB_ID             = 0x08U

} HAL_ETH_CallbackIDTypeDef;


typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth);

#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */


typedef struct

{

  FunctionalState PromiscuousMode;

  FunctionalState ReceiveAllMode;

  FunctionalState HachOrPerfectFilter;

  FunctionalState HashUnicast;

  FunctionalState HashMulticast;

  FunctionalState PassAllMulticast;

  FunctionalState SrcAddrFiltering;

  FunctionalState SrcAddrInverseFiltering;

  FunctionalState DestAddrInverseFiltering;

  FunctionalState BroadcastFilter;

  uint32_t        ControlPacketsFilter;

} ETH_MACFilterConfigTypeDef;


typedef struct

{

  FunctionalState WakeUpPacket;

  FunctionalState MagicPacket;

  FunctionalState GlobalUnicast;

  FunctionalState WakeUpForward;

} ETH_PowerDownConfigTypeDef;


/* Exported constants --------------------------------------------------------*/

/*

   DMA Tx Normal Descriptor Read Format

  -----------------------------------------------------------------------------------------------

  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |

  -----------------------------------------------------------------------------------------------

  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |

  -----------------------------------------------------------------------------------------------

  TDES2 |                         Buffer1 Address [31:0]                                         |

  -----------------------------------------------------------------------------------------------

  TDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |

  -----------------------------------------------------------------------------------------------

*/


#define ETH_DMATXDESC_OWN                     0x80000000U

#define ETH_DMATXDESC_IC                      0x40000000U

#define ETH_DMATXDESC_LS                      0x20000000U

#define ETH_DMATXDESC_FS                      0x10000000U

#define ETH_DMATXDESC_DC                      0x08000000U

#define ETH_DMATXDESC_DP                      0x04000000U

#define ETH_DMATXDESC_TTSE                    0x02000000U

#define ETH_DMATXDESC_CIC                     0x00C00000U

#define ETH_DMATXDESC_CIC_BYPASS              0x00000000U

#define ETH_DMATXDESC_CIC_IPV4HEADER          0x00400000U

#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  0x00800000U

#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     0x00C00000U

#define ETH_DMATXDESC_TER                     0x00200000U

#define ETH_DMATXDESC_TCH                     0x00100000U

#define ETH_DMATXDESC_TTSS                    0x00020000U

#define ETH_DMATXDESC_IHE                     0x00010000U

#define ETH_DMATXDESC_ES                      0x00008000U

#define ETH_DMATXDESC_JT                      0x00004000U

#define ETH_DMATXDESC_FF                      0x00002000U

#define ETH_DMATXDESC_PCE                     0x00001000U

#define ETH_DMATXDESC_LCA                     0x00000800U

#define ETH_DMATXDESC_NC                      0x00000400U

#define ETH_DMATXDESC_LCO                     0x00000200U

#define ETH_DMATXDESC_EC                      0x00000100U

#define ETH_DMATXDESC_VF                      0x00000080U

#define ETH_DMATXDESC_CC                      0x00000078U

#define ETH_DMATXDESC_ED                      0x00000004U

#define ETH_DMATXDESC_UF                      0x00000002U

#define ETH_DMATXDESC_DB                      0x00000001U

#define ETH_DMATXDESC_TBS2                    0x1FFF0000U

#define ETH_DMATXDESC_TBS1                    0x00001FFFU

#define ETH_DMATXDESC_B1AP                    0xFFFFFFFFU

#define ETH_DMATXDESC_B2AP                    0xFFFFFFFFU

/*---------------------------------------------------------------------------------------------

TDES6 |                         Transmit Time Stamp Low [31:0]                                 |

-----------------------------------------------------------------------------------------------

TDES7 |                         Transmit Time Stamp High [31:0]                                |

----------------------------------------------------------------------------------------------*/


/* Bit definition of TDES6 register */

#define ETH_DMAPTPTXDESC_TTSL                 0xFFFFFFFFU  /* Transmit Time Stamp Low */


/* Bit definition of TDES7 register */

#define ETH_DMAPTPTXDESC_TTSH                 0xFFFFFFFFU  /* Transmit Time Stamp High */


/*

  DMA Rx Normal Descriptor read format

  --------------------------------------------------------------------------------------------------------------------

  RDES0 | OWN(31) |                                             Status [30:0]                                          |

  ---------------------------------------------------------------------------------------------------------------------

  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |

  ---------------------------------------------------------------------------------------------------------------------

  RDES2 |                                       Buffer1 Address [31:0]                                                 |

  ---------------------------------------------------------------------------------------------------------------------

  RDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                             |

  ---------------------------------------------------------------------------------------------------------------------

*/


#define ETH_DMARXDESC_OWN         0x80000000U

#define ETH_DMARXDESC_AFM         0x40000000U

#define ETH_DMARXDESC_FL          0x3FFF0000U

#define ETH_DMARXDESC_ES          0x00008000U

#define ETH_DMARXDESC_DE          0x00004000U

#define ETH_DMARXDESC_SAF         0x00002000U

#define ETH_DMARXDESC_LE          0x00001000U

#define ETH_DMARXDESC_OE          0x00000800U

#define ETH_DMARXDESC_VLAN        0x00000400U

#define ETH_DMARXDESC_FS          0x00000200U

#define ETH_DMARXDESC_LS          0x00000100U

#define ETH_DMARXDESC_IPV4HCE     0x00000080U

#define ETH_DMARXDESC_LC          0x00000040U

#define ETH_DMARXDESC_FT          0x00000020U

#define ETH_DMARXDESC_RWT         0x00000010U

#define ETH_DMARXDESC_RE          0x00000008U

#define ETH_DMARXDESC_DBE         0x00000004U

#define ETH_DMARXDESC_CE          0x00000002U

#define ETH_DMARXDESC_MAMPCE      0x00000001U

#define ETH_DMARXDESC_DIC         0x80000000U

#define ETH_DMARXDESC_RBS2        0x1FFF0000U

#define ETH_DMARXDESC_RER         0x00008000U

#define ETH_DMARXDESC_RCH         0x00004000U

#define ETH_DMARXDESC_RBS1        0x00001FFFU

#define ETH_DMARXDESC_B1AP        0xFFFFFFFFU

#define ETH_DMARXDESC_B2AP        0xFFFFFFFFU

/*---------------------------------------------------------------------------------------------------------------------

  RDES4 |                   Reserved[31:15]              |             Extended Status [14:0]                          |

  ---------------------------------------------------------------------------------------------------------------------

  RDES5 |                                            Reserved[31:0]                                                    |

  ---------------------------------------------------------------------------------------------------------------------

  RDES6 |                                       Receive Time Stamp Low [31:0]                                          |

  ---------------------------------------------------------------------------------------------------------------------

  RDES7 |                                       Receive Time Stamp High [31:0]                                         |

  --------------------------------------------------------------------------------------------------------------------*/


/* Bit definition of RDES4 register */

#define ETH_DMAPTPRXDESC_PTPV                            0x00002000U  /* PTP Version */

#define ETH_DMAPTPRXDESC_PTPFT                           0x00001000U  /* PTP Frame Type */

#define ETH_DMAPTPRXDESC_PTPMT                           0x00000F00U  /* PTP Message Type */

#define ETH_DMAPTPRXDESC_PTPMT_SYNC                      0x00000100U  /* SYNC message

                                                                                   (all clock types) */

#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP                  0x00000200U  /* FollowUp message

                                                                                   (all clock types) */

#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ                  0x00000300U  /* DelayReq message

                                                                                   (all clock types) */

#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP                 0x00000400U  /* DelayResp message

                                                                                   (all clock types) */

#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE        0x00000500U  /* PdelayReq message

                                                                                   (peer-to-peer transparent clock)

                                                                                    or Announce message (Ordinary

                                                                                    or Boundary clock) */

#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG          0x00000600U  /* PdelayResp message

                                                                                   (peer-to-peer transparent clock)

                                                                                    or Management message (Ordinary

                                                                                    or Boundary clock)  */

#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U  /* PdelayRespFollowUp message

                                                                                  (peer-to-peer transparent clock)

                                                                                   or Signaling message (Ordinary

                                                                                   or Boundary clock) */

#define ETH_DMAPTPRXDESC_IPV6PR                          0x00000080U  /* IPv6 Packet Received */

#define ETH_DMAPTPRXDESC_IPV4PR                          0x00000040U  /* IPv4 Packet Received */

#define ETH_DMAPTPRXDESC_IPCB                            0x00000020U  /* IP Checksum Bypassed */

#define ETH_DMAPTPRXDESC_IPPE                            0x00000010U  /* IP Payload Error */

#define ETH_DMAPTPRXDESC_IPHE                            0x00000008U  /* IP Header Error */

#define ETH_DMAPTPRXDESC_IPPT                            0x00000007U  /* IP Payload Type */

#define ETH_DMAPTPRXDESC_IPPT_UDP                        0x00000001U  /* UDP payload encapsulated in

                                                                                   the IP datagram */

#define ETH_DMAPTPRXDESC_IPPT_TCP                        0x00000002U  /* TCP payload encapsulated in

                                                                                   the IP datagram */

#define ETH_DMAPTPRXDESC_IPPT_ICMP                       0x00000003U  /* ICMP payload encapsulated in

                                                                                     the IP datagram */


/* Bit definition of RDES6 register */

#define ETH_DMAPTPRXDESC_RTSL  0xFFFFFFFFU  /* Receive Time Stamp Low */


/* Bit definition of RDES7 register */

#define ETH_DMAPTPRXDESC_RTSH  0xFFFFFFFFU  /* Receive Time Stamp High */


#define ETH_MAX_PACKET_SIZE      1528U

#define ETH_HEADER               14U

#define ETH_CRC                  4U

#define ETH_VLAN_TAG             4U

#define ETH_MIN_PAYLOAD          46U

#define ETH_MAX_PAYLOAD          1500U

#define ETH_JUMBO_FRAME_PAYLOAD  9000U

#define HAL_ETH_ERROR_NONE             0x00000000U

#define HAL_ETH_ERROR_PARAM            0x00000001U

#define HAL_ETH_ERROR_BUSY             0x00000002U

#define HAL_ETH_ERROR_TIMEOUT          0x00000004U

#define HAL_ETH_ERROR_DMA              0x00000008U

#define HAL_ETH_ERROR_MAC              0x00000010U

#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

#define HAL_ETH_ERROR_INVALID_CALLBACK 0x00000020U

#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */

#define ETH_TX_PACKETS_FEATURES_CSUM          0x00000001U

#define ETH_TX_PACKETS_FEATURES_SAIC          0x00000002U

#define ETH_TX_PACKETS_FEATURES_VLANTAG       0x00000004U

#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  0x00000008U

#define ETH_TX_PACKETS_FEATURES_TSO           0x00000010U

#define ETH_TX_PACKETS_FEATURES_CRCPAD        0x00000020U

#define ETH_CRC_PAD_DISABLE      (uint32_t)(ETH_DMATXDESC_DP | ETH_DMATXDESC_DC)

#define ETH_CRC_PAD_INSERT       0x00000000U

#define ETH_CRC_INSERT           ETH_DMATXDESC_DP

#define ETH_CHECKSUM_DISABLE                         ETH_DMATXDESC_CIC_BYPASS

#define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXDESC_CIC_IPV4HEADER

#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT

#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXDESC_CIC_TCPUDPICMP_FULL

#define ETH_VLAN_FILTER_PASS        ETH_DMARXDESC_VLAN

#define ETH_DEST_ADDRESS_FAIL       ETH_DMARXDESC_AFM

#define ETH_SOURCE_ADDRESS_FAIL     ETH_DMARXDESC_SAF

#define ETH_DRIBBLE_BIT_ERROR   ETH_DMARXDESC_DBE

#define ETH_RECEIVE_ERROR       ETH_DMARXDESC_RE

#define ETH_RECEIVE_OVERFLOW    ETH_DMARXDESC_OE

#define ETH_WATCHDOG_TIMEOUT    ETH_DMARXDESC_RWT

#define ETH_GIANT_PACKET        ETH_DMARXDESC_IPV4HC

#define ETH_CRC_ERROR           ETH_DMARXDESC_CE

#define ETH_DMAARBITRATION_RX        ETH_DMABMR_DA

#define ETH_DMAARBITRATION_RX1_TX1   0x00000000U

#define ETH_DMAARBITRATION_RX2_TX1   ETH_DMABMR_RTPR_2_1

#define ETH_DMAARBITRATION_RX3_TX1   ETH_DMABMR_RTPR_3_1

#define ETH_DMAARBITRATION_RX4_TX1   ETH_DMABMR_RTPR_4_1

#define ETH_DMAARBITRATION_TX        (ETH_DMAMR_TXPR | ETH_DMAMR_DA)

#define ETH_DMAARBITRATION_TX1_RX1   0x00000000U

#define ETH_DMAARBITRATION_TX2_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)

#define ETH_DMAARBITRATION_TX3_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)

#define ETH_DMAARBITRATION_TX4_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)

#define ETH_DMAARBITRATION_TX5_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)

#define ETH_DMAARBITRATION_TX6_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)

#define ETH_DMAARBITRATION_TX7_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)

#define ETH_DMAARBITRATION_TX8_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)

#define ETH_BURSTLENGTH_FIXED           ETH_DMABMR_FB

#define ETH_BURSTLENGTH_MIXED           ETH_DMABMR_MB

#define ETH_BURSTLENGTH_UNSPECIFIED     0x00000000U

#define ETH_TXDMABURSTLENGTH_1BEAT          0x00000100U

#define ETH_TXDMABURSTLENGTH_2BEAT          0x00000200U

#define ETH_TXDMABURSTLENGTH_4BEAT          0x00000400U

#define ETH_TXDMABURSTLENGTH_8BEAT          0x00000800U

#define ETH_TXDMABURSTLENGTH_16BEAT         0x00001000U

#define ETH_TXDMABURSTLENGTH_32BEAT         0x00002000U

#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT    0x01000100U

#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT    0x01000200U

#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT   0x01000400U

#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT   0x01000800U

#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT   0x01001000U

#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT  0x01002000U

#define ETH_RXDMABURSTLENGTH_1BEAT          0x00020000U

#define ETH_RXDMABURSTLENGTH_2BEAT          0x00040000U

#define ETH_RXDMABURSTLENGTH_4BEAT          0x00080000U

#define ETH_RXDMABURSTLENGTH_8BEAT          0x00100000U

#define ETH_RXDMABURSTLENGTH_16BEAT         0x00200000U

#define ETH_RXDMABURSTLENGTH_32BEAT         0x00400000U

#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT    0x01020000U

#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT    0x01040000U

#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT   0x01080000U

#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT   0x01100000U

#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT   0x01200000U

#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT  0x01400000U

#define ETH_DMA_NORMAL_IT                 ETH_DMAIER_NISE

#define ETH_DMA_ABNORMAL_IT               ETH_DMAIER_AISE

#define ETH_DMA_FATAL_BUS_ERROR_IT        ETH_DMAIER_FBEIE

#define ETH_DMA_EARLY_RX_IT               ETH_DMAIER_ERIE

#define ETH_DMA_EARLY_TX_IT               ETH_DMAIER_ETIE

#define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT    ETH_DMAIER_RWTIE

#define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMAIER_RPSIE

#define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT  ETH_DMAIER_RBUIE

#define ETH_DMA_RX_IT                     ETH_DMAIER_RIE

#define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT  ETH_DMAIER_TBUIE

#define ETH_DMA_TX_PROCESS_STOPPED_IT     ETH_DMAIER_TPSIE

#define ETH_DMA_TX_IT                     ETH_DMAIER_TIE

#define ETH_DMA_NO_ERROR_FLAG                     0x00000000U

#define ETH_DMA_TX_DATA_TRANS_ERROR_FLAG          ETH_DMASR_EBS_DataTransfTx

#define ETH_DMA_RX_DATA_TRANS_ERROR_FLAG          0x00000000U

#define ETH_DMA_READ_TRANS_ERROR_FLAG             ETH_DMASR_EBS_ReadTransf

#define ETH_DMA_WRITE_TRANS_ERROR_FLAG            0x00000000U

#define ETH_DMA_DESC_ACCESS_ERROR_FLAG            ETH_DMASR_EBS_DescAccess

#define ETH_DMA_DATA_BUFF_ACCESS_ERROR_FLAG       0x00000000U

#define ETH_DMA_FATAL_BUS_ERROR_FLAG              ETH_DMASR_FBES

#define ETH_DMA_EARLY_TX_IT_FLAG                  ETH_DMASR_ETS

#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG          ETH_DMASR_RWTS

#define ETH_DMA_RX_PROCESS_STOPPED_FLAG           ETH_DMASR_RPSS

#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG        ETH_DMASR_RBUS

#define ETH_DMA_TX_PROCESS_STOPPED_FLAG           ETH_DMASR_TPS

#define ETH_TRANSMITSTOREFORWARD       ETH_DMAOMR_TSF

#define ETH_TRANSMITTHRESHOLD_16       ETH_DMAOMR_TTC_16Bytes

#define ETH_TRANSMITTHRESHOLD_24       ETH_DMAOMR_TTC_24Bytes

#define ETH_TRANSMITTHRESHOLD_32       ETH_DMAOMR_TTC_32Bytes

#define ETH_TRANSMITTHRESHOLD_40       ETH_DMAOMR_TTC_40Bytes

#define ETH_TRANSMITTHRESHOLD_64       ETH_DMAOMR_TTC_64Bytes

#define ETH_TRANSMITTHRESHOLD_128      ETH_DMAOMR_TTC_128Bytes

#define ETH_TRANSMITTHRESHOLD_192      ETH_DMAOMR_TTC_192Bytes

#define ETH_TRANSMITTHRESHOLD_256      ETH_DMAOMR_TTC_256Bytes

#define ETH_RECEIVESTOREFORWARD        ETH_DMAOMR_RSF

#define ETH_RECEIVETHRESHOLD8_64       ETH_DMAOMR_RTC_64Bytes

#define ETH_RECEIVETHRESHOLD8_32       ETH_DMAOMR_RTC_32Bytes

#define ETH_RECEIVETHRESHOLD8_96       ETH_DMAOMR_RTC_96Bytes

#define ETH_RECEIVETHRESHOLD8_128      ETH_DMAOMR_RTC_128Bytes

#define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACFCR_PLT_Minus4

#define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACFCR_PLT_Minus28

#define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACFCR_PLT_Minus144

#define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACFCR_PLT_Minus256

#define ETH_SPEED_10M        0x00000000U

#define ETH_SPEED_100M       0x00004000U

#define ETH_FULLDUPLEX_MODE       ETH_MACCR_DM

#define ETH_HALFDUPLEX_MODE       0x00000000U

#define ETH_BACKOFFLIMIT_10  0x00000000U

#define ETH_BACKOFFLIMIT_8   0x00000020U

#define ETH_BACKOFFLIMIT_4   0x00000040U

#define ETH_BACKOFFLIMIT_1   0x00000060U

#define ETH_SOURCEADDRESS_DISABLE           0x00000000U

#define ETH_SOURCEADDRESS_INSERT_ADDR0      ETH_MACCR_SARC_INSADDR0

#define ETH_SOURCEADDRESS_INSERT_ADDR1      ETH_MACCR_SARC_INSADDR1

#define ETH_SOURCEADDRESS_REPLACE_ADDR0     ETH_MACCR_SARC_REPADDR0

#define ETH_SOURCEADDRESS_REPLACE_ADDR1     ETH_MACCR_SARC_REPADDR1

#define ETH_VLANTAGCOMPARISON_12BIT    0x00010000U

#define ETH_VLANTAGCOMPARISON_16BIT    0x00000000U

#define ETH_MAC_ADDRESS0     0x00000000U

#define ETH_MAC_ADDRESS1     0x00000008U

#define ETH_MAC_ADDRESS2     0x00000010U

#define ETH_MAC_ADDRESS3     0x00000018U

#define ETH_MAC_PMT_IT           ETH_MACSR_PMTS

#define ETH_WAKEUP_FRAME_RECIEVED     ETH_MACPMTCSR_WFR

#define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPMTCSR_MPR

#define HAL_ETH_STATE_RESET       0x00000000U

#define HAL_ETH_STATE_READY       0x00000010U

#define HAL_ETH_STATE_BUSY        0x00000023U

#define HAL_ETH_STATE_STARTED     0x00000023U

#define HAL_ETH_STATE_ERROR       0x000000E0U

#define ETH_AUTONEGOTIATION_ENABLE     0x00000001U

#define ETH_AUTONEGOTIATION_DISABLE    0x00000000U


#define ETH_RXPOLLING_MODE      0x00000000U

#define ETH_RXINTERRUPT_MODE    0x00000001U

#define ETH_CHECKSUM_BY_HARDWARE      0x00000000U

#define ETH_CHECKSUM_BY_SOFTWARE      0x00000001U

#define ETH_MEDIA_INTERFACE_MII       0x00000000U

#define ETH_MEDIA_INTERFACE_RMII      (SYSCFG_PMC_MII_RMII_SEL)

#define ETH_WATCHDOG_ENABLE       0x00000000U

#define ETH_WATCHDOG_DISABLE      0x00800000U

#define ETH_JABBER_ENABLE    0x00000000U

#define ETH_JABBER_DISABLE   0x00400000U

#define ETH_INTERFRAMEGAP_96BIT   0x00000000U

#define ETH_INTERFRAMEGAP_88BIT   0x00020000U

#define ETH_INTERFRAMEGAP_80BIT   0x00040000U

#define ETH_INTERFRAMEGAP_72BIT   0x00060000U

#define ETH_INTERFRAMEGAP_64BIT   0x00080000U

#define ETH_INTERFRAMEGAP_56BIT   0x000A0000U

#define ETH_INTERFRAMEGAP_48BIT   0x000C0000U

#define ETH_INTERFRAMEGAP_40BIT   0x000E0000U

#define ETH_CARRIERSENCE_ENABLE   0x00000000U

#define ETH_CARRIERSENCE_DISABLE  0x00010000U

#define ETH_RECEIVEOWN_ENABLE     0x00000000U

#define ETH_RECEIVEOWN_DISABLE    0x00002000U

#define ETH_LOOPBACKMODE_ENABLE        0x00001000U

#define ETH_LOOPBACKMODE_DISABLE       0x00000000U

#define ETH_CHECKSUMOFFLAOD_ENABLE     0x00000400U

#define ETH_CHECKSUMOFFLAOD_DISABLE    0x00000000U

#define ETH_RETRYTRANSMISSION_ENABLE   0x00000000U

#define ETH_RETRYTRANSMISSION_DISABLE  0x00000200U

#define ETH_AUTOMATICPADCRCSTRIP_ENABLE     0x00000080U

#define ETH_AUTOMATICPADCRCSTRIP_DISABLE    0x00000000U

#define ETH_DEFFERRALCHECK_ENABLE       0x00000010U

#define ETH_DEFFERRALCHECK_DISABLE      0x00000000U

#define ETH_RECEIVEALL_ENABLE     0x80000000U

#define ETH_RECEIVEALL_DISABLE    0x00000000U

#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE       0x00000200U

#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE      0x00000300U

#define ETH_SOURCEADDRFILTER_DISABLE             0x00000000U

#define ETH_PASSCONTROLFRAMES_BLOCKALL                0x00000040U

#define ETH_PASSCONTROLFRAMES_FORWARDALL              0x00000080U

#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U

#define ETH_BROADCASTFRAMESRECEPTION_ENABLE     0x00000000U

#define ETH_BROADCASTFRAMESRECEPTION_DISABLE    0x00000020U

#define ETH_DESTINATIONADDRFILTER_NORMAL    0x00000000U

#define ETH_DESTINATIONADDRFILTER_INVERSE   0x00000008U

#define ETH_PROMISCUOUS_MODE_ENABLE     0x00000001U

#define ETH_PROMISCUOUS_MODE_DISABLE    0x00000000U

#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE    0x00000404U

#define ETH_MULTICASTFRAMESFILTER_HASHTABLE           0x00000004U

#define ETH_MULTICASTFRAMESFILTER_PERFECT             0x00000000U

#define ETH_MULTICASTFRAMESFILTER_NONE                0x00000010U

#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U

#define ETH_UNICASTFRAMESFILTER_HASHTABLE        0x00000002U

#define ETH_UNICASTFRAMESFILTER_PERFECT          0x00000000U

#define ETH_ZEROQUANTAPAUSE_ENABLE     0x00000000U

#define ETH_ZEROQUANTAPAUSE_DISABLE    0x00000080U

#define ETH_PAUSELOWTHRESHOLD_MINUS4        0x00000000U

#define ETH_PAUSELOWTHRESHOLD_MINUS28       0x00000010U

#define ETH_PAUSELOWTHRESHOLD_MINUS144      0x00000020U

#define ETH_PAUSELOWTHRESHOLD_MINUS256      0x00000030U

#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE  0x00000008U

#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U

#define ETH_RECEIVEFLOWCONTROL_ENABLE       0x00000004U

#define ETH_RECEIVEFLOWCONTROL_DISABLE      0x00000000U

#define ETH_TRANSMITFLOWCONTROL_ENABLE      0x00000002U

#define ETH_TRANSMITFLOWCONTROL_DISABLE     0x00000000U

#define ETH_MAC_ADDRESSFILTER_SA       0x00000000U

#define ETH_MAC_ADDRESSFILTER_DA       0x00000008U

#define ETH_MAC_ADDRESSMASK_BYTE6      0x20000000U

#define ETH_MAC_ADDRESSMASK_BYTE5      0x10000000U

#define ETH_MAC_ADDRESSMASK_BYTE4      0x08000000U

#define ETH_MAC_ADDRESSMASK_BYTE3      0x04000000U

#define ETH_MAC_ADDRESSMASK_BYTE2      0x02000000U

#define ETH_MAC_ADDRESSMASK_BYTE1      0x01000000U

#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES     0x00000000U

#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES    0x00004000U

#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES    0x00008000U

#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES    0x0000C000U

#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES     0x00010000U

#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES     0x00014000U

#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES     0x00018000U

#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES     0x0001C000U

#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES      0x00000000U

#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES      0x00000008U

#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES      0x00000010U

#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES     0x00000018U

#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1   0x00000000U

#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1   0x00004000U

#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1   0x00008000U

#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1   0x0000C000U

#define ETH_DMAARBITRATION_RXPRIORTX             0x00000002U

#define ETH_DMATXDESC_LASTSEGMENTS      0x40000000U

#define ETH_DMATXDESC_FIRSTSEGMENT      0x20000000U

#define ETH_DMATXDESC_CHECKSUMBYPASS             0x00000000U

#define ETH_DMATXDESC_CHECKSUMIPV4HEADER         0x00400000U

#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT  0x00800000U

#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL     0x00C00000U

#define ETH_DMARXDESC_BUFFER1     0x00000000U

#define ETH_DMARXDESC_BUFFER2     0x00000001U

#define ETH_PMT_FLAG_WUFFRPR      0x80000000U

#define ETH_PMT_FLAG_WUFR         0x00000040U

#define ETH_PMT_FLAG_MPR          0x00000020U

#define ETH_MMC_IT_TGF       0x00200000U

#define ETH_MMC_IT_TGFMSC    0x00008000U

#define ETH_MMC_IT_TGFSC     0x00004000U

#define ETH_MMC_IT_RGUF      0x10020000U

#define ETH_MMC_IT_RFAE      0x10000040U

#define ETH_MMC_IT_RFCE      0x10000020U

#define ETH_MAC_FLAG_TST     0x00000200U

#define ETH_MAC_FLAG_MMCT    0x00000040U

#define ETH_MAC_FLAG_MMCR    0x00000020U

#define ETH_MAC_FLAG_MMC     0x00000010U

#define ETH_MAC_FLAG_PMT     0x00000008U

#define ETH_DMA_FLAG_TST               0x20000000U

#define ETH_DMA_FLAG_PMT               0x10000000U

#define ETH_DMA_FLAG_MMC               0x08000000U

#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U

#define ETH_DMA_FLAG_READWRITEERROR    0x01000000U

#define ETH_DMA_FLAG_ACCESSERROR       0x02000000U

#define ETH_DMA_FLAG_NIS               0x00010000U

#define ETH_DMA_FLAG_AIS               0x00008000U

#define ETH_DMA_FLAG_ER                0x00004000U

#define ETH_DMA_FLAG_FBE               0x00002000U

#define ETH_DMA_FLAG_ET                0x00000400U

#define ETH_DMA_FLAG_RWT               0x00000200U

#define ETH_DMA_FLAG_RPS               0x00000100U

#define ETH_DMA_FLAG_RBU               0x00000080U

#define ETH_DMA_FLAG_R                 0x00000040U

#define ETH_DMA_FLAG_TU                0x00000020U

#define ETH_DMA_FLAG_RO                0x00000010U

#define ETH_DMA_FLAG_TJT               0x00000008U

#define ETH_DMA_FLAG_TBU               0x00000004U

#define ETH_DMA_FLAG_TPS               0x00000002U

#define ETH_DMA_FLAG_T                 0x00000001U

#define ETH_MAC_IT_TST       0x00000200U

#define ETH_MAC_IT_MMCT      0x00000040U

#define ETH_MAC_IT_MMCR      0x00000020U

#define ETH_MAC_IT_MMC       0x00000010U

#define ETH_MAC_IT_PMT       0x00000008U

#define ETH_DMA_IT_TST       0x20000000U

#define ETH_DMA_IT_PMT       0x10000000U

#define ETH_DMA_IT_MMC       0x08000000U

#define ETH_DMA_IT_NIS       0x00010000U

#define ETH_DMA_IT_AIS       0x00008000U

#define ETH_DMA_IT_ER        0x00004000U

#define ETH_DMA_IT_FBE       0x00002000U

#define ETH_DMA_IT_ET        0x00000400U

#define ETH_DMA_IT_RWT       0x00000200U

#define ETH_DMA_IT_RPS       0x00000100U

#define ETH_DMA_IT_RBU       0x00000080U

#define ETH_DMA_IT_R         0x00000040U

#define ETH_DMA_IT_TU        0x00000020U

#define ETH_DMA_IT_RO        0x00000010U

#define ETH_DMA_IT_TJT       0x00000008U

#define ETH_DMA_IT_TBU       0x00000004U

#define ETH_DMA_IT_TPS       0x00000002U

#define ETH_DMA_IT_T         0x00000001U

#define ETH_DMA_TRANSMITPROCESS_STOPPED     0x00000000U

#define ETH_DMA_TRANSMITPROCESS_FETCHING    0x00100000U

#define ETH_DMA_TRANSMITPROCESS_WAITING     0x00200000U

#define ETH_DMA_TRANSMITPROCESS_READING     0x00300000U

#define ETH_DMA_TRANSMITPROCESS_SUSPENDED   0x00600000U

#define ETH_DMA_TRANSMITPROCESS_CLOSING     0x00700000U

#define ETH_DMA_RECEIVEPROCESS_STOPPED      0x00000000U

#define ETH_DMA_RECEIVEPROCESS_FETCHING     0x00020000U

#define ETH_DMA_RECEIVEPROCESS_WAITING      0x00060000U

#define ETH_DMA_RECEIVEPROCESS_SUSPENDED    0x00080000U

#define ETH_DMA_RECEIVEPROCESS_CLOSING      0x000A0000U

#define ETH_DMA_RECEIVEPROCESS_QUEUING      0x000E0000U

#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER      0x10000000U

#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U

#define HAL_ETH_PTP_NOT_CONFIGURED        0x00000000U

#define HAL_ETH_PTP_CONFIGURED            0x00000001U


/* Exported macro ------------------------------------------------------------*/


#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \

                                                      (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \


                                                      (__HANDLE__)->MspInitCallback = NULL;             \

                                                      (__HANDLE__)->MspDeInitCallback = NULL;           \


                                                    } while(0)

#else

#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \

                                                      (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \

                                                    } while(0)

#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */


#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMAIER \

                                                                            |= (__INTERRUPT__))


#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMAIER \

                                                                            &= ~(__INTERRUPT__))


#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMAIER &\

                                                                      (__INTERRUPT__)) == (__INTERRUPT__))


#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMASR &\


                                                               (__INTERRUPT__)) == (__INTERRUPT__))


#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMASR = (__INTERRUPT__))


#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMASR &\

                                                                         ( __FLAG__)) == ( __FLAG__))


#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                   ((__HANDLE__)->Instance->DMASR = ( __FLAG__))


#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                     (((__HANDLE__)->Instance->MACSR &\

                                                                              ( __INTERRUPT__)) == ( __INTERRUPT__))


#define ETH_WAKEUP_EXTI_LINE  0x00080000U


#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI->IMR |= (__EXTI_LINE__))


#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI->PR & (__EXTI_LINE__))


#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))


#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR &= ~(__EXTI_LINE__)); \

  (EXTI->RTSR |= (__EXTI_LINE__))


#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR &= ~(__EXTI_LINE__));\

  (EXTI->FTSR |= (__EXTI_LINE__))


#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR |= (__EXTI_LINE__));\

  (EXTI->FTSR |= (__EXTI_LINE__))


#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))


#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->PTPTSCR) & \

                                                           (__FLAG__)) == (__FLAG__)) ? SET : RESET)


#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->PTPTSCR |= (__FLAG__))


/* Exported functions --------------------------------------------------------*/


/* Initialization and de initialization functions  **********************************/

HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);

void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);

void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);


/* Callbacks Register/UnRegister functions  ***********************************/

#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,

                                           pETH_CallbackTypeDef pCallback);

HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);

#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */


/* IO operation functions *******************************************************/

HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);


HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff);

HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,

                                                     pETH_rxAllocateCallbackTypeDef rxAllocateCallback);

HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);

HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode);

HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);

HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);


#ifdef HAL_ETH_USE_PTP

HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);

HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);

HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);

HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);

HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,

                                            ETH_TimeTypeDef *timeoffset);

HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);

HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);

HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback);

HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);

#endif /* HAL_ETH_USE_PTP */


HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout);

HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig);


HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,

                                           uint32_t RegValue);

HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,

                                          uint32_t *pRegValue);


void              HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);

void              HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);

void              HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);

void              HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);

void              HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);

void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);

void              HAL_ETH_RxAllocateCallback(uint8_t **buff);

void              HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length);

void              HAL_ETH_TxFreeCallback(uint32_t *buff);

void              HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp);

/* Peripheral Control functions  **********************************************/

/* MAC & DMA Configuration APIs  **********************************************/

HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);

HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);

HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);

HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);

void              HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);


/* MAC VLAN Processing APIs    ************************************************/

void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits,

                                              uint32_t VLANIdentifier);


/* MAC L2 Packet Filtering APIs  **********************************************/

HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);

HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig);

HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);

HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,

                                                const uint8_t *pMACAddr);


/* MAC Power Down APIs    *****************************************************/

void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth,

                                             const ETH_PowerDownConfigTypeDef *pPowerDownConfig);

void              HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);

HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);


/* Peripheral State functions  **************************************************/

HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth);

uint32_t             HAL_ETH_GetError(const ETH_HandleTypeDef *heth);

uint32_t             HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);

uint32_t             HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);

uint32_t             HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);

#endif /* ETH */


#ifdef __cplusplus

}

#endif


#endif /* STM32F4xx_HAL_ETH_H */

HAL_ETH_MspDeInit
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
DeInitializes ETH MSP.
Definition stm32f4xx_hal_eth.c:481

HAL_ETH_MspInit
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
Initializes the ETH MSP.
Definition stm32f4xx_hal_eth.c:466

HAL_ETH_Init
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
Initialize the Ethernet peripheral registers.
Definition stm32f4xx_hal_eth.c:336

HAL_ETH_DeInit
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
DeInitializes the ETH peripheral.
Definition stm32f4xx_hal_eth.c:433

HAL_ETH_TxFreeCallback
void HAL_ETH_TxFreeCallback(uint32_t *buff)
Tx Free callback.
Definition stm32f4xx_hal_eth.c:1430

HAL_ETH_RxAllocateCallback
void HAL_ETH_RxAllocateCallback(uint8_t **buff)
Rx Allocate callback.
Definition stm32f4xx_hal_eth.c:1311

HAL_ETH_Transmit_IT
HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig)
Sends an Ethernet Packet in interrupt mode.
Definition stm32f4xx_hal_eth.c:1031

HAL_ETH_Start
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
Enables Ethernet MAC and DMA reception and transmission.
Definition stm32f4xx_hal_eth.c:708

HAL_ETH_UnRegisterRxAllocateCallback
HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth)
Unregister the Rx alloc callback.
Definition stm32f4xx_hal_eth.c:1298

HAL_ETH_ReleaseTxPacket
HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
Release transmitted Tx packets.
Definition stm32f4xx_hal_eth.c:1445

HAL_ETH_Transmit
HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout)
Sends an Ethernet Packet in polling mode.
Definition stm32f4xx_hal_eth.c:956

HAL_ETH_Stop_IT
HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
Stop Ethernet MAC and DMA reception/transmission in Interrupt mode.
Definition stm32f4xx_hal_eth.c:886

HAL_ETH_TxPtpCallback
void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp)

HAL_ETH_WritePHYRegister
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
Writes to a PHY register.
Definition stm32f4xx_hal_eth.c:2132

HAL_ETH_RegisterRxLinkCallback
HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback)
Set the Rx link data function.
Definition stm32f4xx_hal_eth.c:1347

HAL_ETH_RegisterTxFreeCallback
HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback)
Set the Tx free function.
Definition stm32f4xx_hal_eth.c:1397

HAL_ETH_UnRegisterTxFreeCallback
HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth)
Unregister the Tx free callback.
Definition stm32f4xx_hal_eth.c:1417

HAL_ETH_RegisterRxAllocateCallback
HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, pETH_rxAllocateCallbackTypeDef rxAllocateCallback)
Register the Rx alloc callback.
Definition stm32f4xx_hal_eth.c:1277

HAL_ETH_Start_IT
HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
Enables Ethernet MAC and DMA reception/transmission in Interrupt mode.
Definition stm32f4xx_hal_eth.c:765

HAL_ETH_ReadPHYRegister
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
Read a PHY register.
Definition stm32f4xx_hal_eth.c:2081

HAL_ETH_GetRxDataErrorCode
HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
Get the error state of the last received packet.
Definition stm32f4xx_hal_eth.c:1382

HAL_ETH_ReadData
HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
Read a received packet.
Definition stm32f4xx_hal_eth.c:1083

HAL_ETH_RxLinkCallback
void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length)
Rx Link callback.
Definition stm32f4xx_hal_eth.c:1328

HAL_ETH_RxCpltCallback
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
Rx Transfer completed callbacks.
Definition stm32f4xx_hal_eth.c:2017

HAL_ETH_WakeUpCallback
void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
ETH WAKEUP interrupt callback.
Definition stm32f4xx_hal_eth.c:2063

HAL_ETH_TxCpltCallback
void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
Tx Transfer completed callbacks.
Definition stm32f4xx_hal_eth.c:2002

HAL_ETH_ErrorCallback
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
Ethernet transfer error callbacks.
Definition stm32f4xx_hal_eth.c:2032

HAL_ETH_PMTCallback
void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
Ethernet Power Management module IT callback.
Definition stm32f4xx_hal_eth.c:2047

HAL_ETH_IRQHandler
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
This function handles ETH interrupt request.
Definition stm32f4xx_hal_eth.c:1890

HAL_ETH_UnRegisterRxLinkCallback
HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth)
Unregister the Rx link callback.
Definition stm32f4xx_hal_eth.c:1367

HAL_ETH_Stop
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
Stop Ethernet MAC and DMA reception/transmission.
Definition stm32f4xx_hal_eth.c:833

HAL_ETH_GetMACFilterConfig
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
Get the ETH MAC (L2) Filters configuration.
Definition stm32f4xx_hal_eth.c:2427

HAL_ETH_GetDMAConfig
HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
Get the configuration of the DMA.
Definition stm32f4xx_hal_eth.c:2243

HAL_ETH_SetWakeUpFilter
HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
Set the WakeUp filter.
Definition stm32f4xx_hal_eth.c:2619

HAL_ETH_GetMACConfig
HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
Get the configuration of the MAC and MTL subsystems.
Definition stm32f4xx_hal_eth.c:2200

HAL_ETH_SetMACFilterConfig
HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig)
Set the ETH MAC (L2) Filters configuration.
Definition stm32f4xx_hal_eth.c:2386

HAL_ETH_SetDMAConfig
HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
Set the ETH DMA configuration.
Definition stm32f4xx_hal_eth.c:2309

HAL_ETH_SetRxVLANIdentifier
void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
Set the VLAN Identifier for Rx packets.
Definition stm32f4xx_hal_eth.c:2536

HAL_ETH_EnterPowerDownMode
void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig)
Enters the Power down mode.
Definition stm32f4xx_hal_eth.c:2564

HAL_ETH_ExitPowerDownMode
void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth)
Exits from the Power down mode.
Definition stm32f4xx_hal_eth.c:2582

HAL_ETH_SetMACConfig
HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
Set the MAC configuration.
Definition stm32f4xx_hal_eth.c:2282

HAL_ETH_SetMDIOClockRange
void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
Configures the Clock range of ETH MDIO interface.
Definition stm32f4xx_hal_eth.c:2334

HAL_ETH_SetSourceMACAddrMatch
HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr, const uint8_t *pMACAddr)
Set the source MAC Address to be matched.
Definition stm32f4xx_hal_eth.c:2464

HAL_ETH_SetHashTable
HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable)
Set the ETH Hash Table Value.
Definition stm32f4xx_hal_eth.c:2500

HAL_ETH_GetState
HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth)
Returns the ETH state.
Definition stm32f4xx_hal_eth.c:2668

HAL_ETH_GetMACWakeUpSource
uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth)
Returns the ETH MAC WakeUp event source.
Definition stm32f4xx_hal_eth.c:2712

HAL_ETH_GetError
uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth)
Returns the ETH error code.
Definition stm32f4xx_hal_eth.c:2679

HAL_ETH_GetDMAError
uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth)
Returns the ETH DMA error code.
Definition stm32f4xx_hal_eth.c:2690

HAL_ETH_GetMACError
uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth)
Returns the ETH MAC error code.
Definition stm32f4xx_hal_eth.c:2701

pETH_rxAllocateCallbackTypeDef
void(* pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer)
HAL ETH Rx Get Buffer Function definition.
Definition stm32f4xx_hal_eth.h:488

ETH_MediaInterfaceTypeDef
ETH_MediaInterfaceTypeDef
HAL ETH Media Interfaces enum definition.
Definition stm32f4xx_hal_eth.h:402

pETH_txFreeCallbackTypeDef
void(* pETH_txFreeCallbackTypeDef)(uint32_t *buffer)
HAL ETH Tx Free Function definition.
Definition stm32f4xx_hal_eth.h:505

pETH_rxLinkCallbackTypeDef
void(* pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length)
HAL ETH Rx Set App Data Function definition.
Definition stm32f4xx_hal_eth.h:496

pETH_txPtpCallbackTypeDef
void(* pETH_txPtpCallbackTypeDef)(uint32_t *buffer, ETH_TimeStampTypeDef *timestamp)
HAL ETH Tx Free Function definition.
Definition stm32f4xx_hal_eth.h:513

ETH_BufferTypeDef
struct __ETH_BufferTypeDef ETH_BufferTypeDef
ETH Buffers List structure definition.

HAL_ETH_StateTypeDef
uint32_t HAL_ETH_StateTypeDef
HAL State structures definition.
Definition stm32f4xx_hal_eth.h:480

HAL_ETH_RMII_MODE
@ HAL_ETH_RMII_MODE
Definition stm32f4xx_hal_eth.h:404

HAL_ETH_MII_MODE
@ HAL_ETH_MII_MODE
Definition stm32f4xx_hal_eth.h:403

ETH_RX_DESC_CNT
#define ETH_RX_DESC_CNT
Definition stm32f4xx_hal_eth.h:46

ETH_TX_DESC_CNT
#define ETH_TX_DESC_CNT
Definition stm32f4xx_hal_eth.h:42

stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.

HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition stm32f4xx_hal_def.h:39

ETH_DMAConfigTypeDef
ETH DMA Configuration Structure definition.
Definition stm32f4xx_hal_eth.h:342

ETH_DMAConfigTypeDef::ReceiveStoreForward
FunctionalState ReceiveStoreForward
Definition stm32f4xx_hal_eth.h:353

ETH_DMAConfigTypeDef::AddressAlignedBeats
FunctionalState AddressAlignedBeats
Definition stm32f4xx_hal_eth.h:346

ETH_DMAConfigTypeDef::ReceiveThresholdControl
uint32_t ReceiveThresholdControl
Definition stm32f4xx_hal_eth.h:378

ETH_DMAConfigTypeDef::SecondFrameOperate
FunctionalState SecondFrameOperate
Definition stm32f4xx_hal_eth.h:383

ETH_DMAConfigTypeDef::DMAArbitration
uint32_t DMAArbitration
Definition stm32f4xx_hal_eth.h:343

ETH_DMAConfigTypeDef::ForwardErrorFrames
FunctionalState ForwardErrorFrames
Definition stm32f4xx_hal_eth.h:370

ETH_DMAConfigTypeDef::RxDMABurstLength
uint32_t RxDMABurstLength
Definition stm32f4xx_hal_eth.h:367

ETH_DMAConfigTypeDef::ForwardUndersizedGoodFrames
FunctionalState ForwardUndersizedGoodFrames
Definition stm32f4xx_hal_eth.h:374

ETH_DMAConfigTypeDef::TransmitThresholdControl
uint32_t TransmitThresholdControl
Definition stm32f4xx_hal_eth.h:362

ETH_DMAConfigTypeDef::EnhancedDescriptorFormat
FunctionalState EnhancedDescriptorFormat
Definition stm32f4xx_hal_eth.h:387

ETH_DMAConfigTypeDef::DescriptorSkipLength
uint32_t DescriptorSkipLength
Definition stm32f4xx_hal_eth.h:390

ETH_DMAConfigTypeDef::DropTCPIPChecksumErrorFrame
FunctionalState DropTCPIPChecksumErrorFrame
Definition stm32f4xx_hal_eth.h:351

ETH_DMAConfigTypeDef::TransmitStoreForward
FunctionalState TransmitStoreForward
Definition stm32f4xx_hal_eth.h:355

ETH_DMAConfigTypeDef::FlushRxPacket
FunctionalState FlushRxPacket
Definition stm32f4xx_hal_eth.h:371

ETH_DMAConfigTypeDef::BurstMode
uint32_t BurstMode
Definition stm32f4xx_hal_eth.h:349

ETH_DMAConfigTypeDef::TxDMABurstLength
uint32_t TxDMABurstLength
Definition stm32f4xx_hal_eth.h:359

ETH_DMADescTypeDef
ETH DMA Descriptor structure definition.
Definition stm32f4xx_hal_eth.h:59

ETH_DMADescTypeDef::DESC1
__IO uint32_t DESC1
Definition stm32f4xx_hal_eth.h:61

ETH_DMADescTypeDef::BackupAddr1
uint32_t BackupAddr1
Definition stm32f4xx_hal_eth.h:69

ETH_DMADescTypeDef::DESC2
__IO uint32_t DESC2
Definition stm32f4xx_hal_eth.h:62

ETH_DMADescTypeDef::DESC5
__IO uint32_t DESC5
Definition stm32f4xx_hal_eth.h:65

ETH_DMADescTypeDef::DESC0
__IO uint32_t DESC0
Definition stm32f4xx_hal_eth.h:60

ETH_DMADescTypeDef::DESC3
__IO uint32_t DESC3
Definition stm32f4xx_hal_eth.h:63

ETH_DMADescTypeDef::DESC6
__IO uint32_t DESC6
Definition stm32f4xx_hal_eth.h:66

ETH_DMADescTypeDef::DESC7
__IO uint32_t DESC7
Definition stm32f4xx_hal_eth.h:67

ETH_DMADescTypeDef::BackupAddr0
uint32_t BackupAddr0
Definition stm32f4xx_hal_eth.h:68

ETH_DMADescTypeDef::DESC4
__IO uint32_t DESC4
Definition stm32f4xx_hal_eth.h:64

ETH_HandleTypeDef
ETH Handle Structure definition.
Definition stm32f4xx_hal_eth.h:527

ETH_HandleTypeDef::Init
ETH_InitTypeDef Init
Definition stm32f4xx_hal_eth.h:530

ETH_HandleTypeDef::gState
__IO HAL_ETH_StateTypeDef gState
Definition stm32f4xx_hal_eth.h:542

ETH_HandleTypeDef::MACErrorCode
__IO uint32_t MACErrorCode
Definition stm32f4xx_hal_eth.h:555

ETH_HandleTypeDef::IsPtpConfigured
__IO uint32_t IsPtpConfigured
Definition stm32f4xx_hal_eth.h:566

ETH_HandleTypeDef::DMAErrorCode
__IO uint32_t DMAErrorCode
Definition stm32f4xx_hal_eth.h:550

ETH_HandleTypeDef::txFreeCallback
pETH_txFreeCallbackTypeDef txFreeCallback
Definition stm32f4xx_hal_eth.h:585

ETH_HandleTypeDef::rxLinkCallback
pETH_rxLinkCallbackTypeDef rxLinkCallback
Definition stm32f4xx_hal_eth.h:584

ETH_HandleTypeDef::MACLPIEvent
__IO uint32_t MACLPIEvent
Definition stm32f4xx_hal_eth.h:563

ETH_HandleTypeDef::Instance
ETH_TypeDef * Instance
Definition stm32f4xx_hal_eth.h:528

ETH_HandleTypeDef::TxDescList
ETH_TxDescListTypeDef TxDescList
Definition stm32f4xx_hal_eth.h:532

ETH_HandleTypeDef::RxDescList
ETH_RxDescListTypeDef RxDescList
Definition stm32f4xx_hal_eth.h:535

ETH_HandleTypeDef::txPtpCallback
pETH_txPtpCallbackTypeDef txPtpCallback
Definition stm32f4xx_hal_eth.h:586

ETH_HandleTypeDef::rxAllocateCallback
pETH_rxAllocateCallbackTypeDef rxAllocateCallback
Definition stm32f4xx_hal_eth.h:583

ETH_HandleTypeDef::MACWakeUpEvent
__IO uint32_t MACWakeUpEvent
Definition stm32f4xx_hal_eth.h:559

ETH_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition stm32f4xx_hal_eth.h:546

ETH_InitTypeDef
ETH Init Structure definition.
Definition stm32f4xx_hal_eth.h:428

ETH_InitTypeDef::TxDesc
ETH_DMADescTypeDef * TxDesc
Definition stm32f4xx_hal_eth.h:435

ETH_InitTypeDef::MediaInterface
ETH_MediaInterfaceTypeDef MediaInterface
Definition stm32f4xx_hal_eth.h:432

ETH_InitTypeDef::RxDesc
ETH_DMADescTypeDef * RxDesc
Definition stm32f4xx_hal_eth.h:438

ETH_InitTypeDef::RxBuffLen
uint32_t RxBuffLen
Definition stm32f4xx_hal_eth.h:440

ETH_InitTypeDef::MACAddr
uint8_t * MACAddr
Definition stm32f4xx_hal_eth.h:430

ETH_MACConfigTypeDef
ETH MAC Configuration Structure definition.
Definition stm32f4xx_hal_eth.h:224

ETH_MACConfigTypeDef::WatchdogTimeout
uint32_t WatchdogTimeout
Definition stm32f4xx_hal_eth.h:297

ETH_MACConfigTypeDef::AutomaticPadCRCStrip
FunctionalState AutomaticPadCRCStrip
Definition stm32f4xx_hal_eth.h:241

ETH_MACConfigTypeDef::UnicastPausePacketDetect
FunctionalState UnicastPausePacketDetect
Definition stm32f4xx_hal_eth.h:317

ETH_MACConfigTypeDef::PauseLowThreshold
uint32_t PauseLowThreshold
Definition stm32f4xx_hal_eth.h:309

ETH_MACConfigTypeDef::PreambleLength
uint32_t PreambleLength
Definition stm32f4xx_hal_eth.h:277

ETH_MACConfigTypeDef::ExtendedInterPacketGap
FunctionalState ExtendedInterPacketGap
Definition stm32f4xx_hal_eth.h:290

ETH_MACConfigTypeDef::ReceiveOwn
FunctionalState ReceiveOwn
Definition stm32f4xx_hal_eth.h:262

ETH_MACConfigTypeDef::RetryTransmission
FunctionalState RetryTransmission
Definition stm32f4xx_hal_eth.h:268

ETH_MACConfigTypeDef::LoopbackMode
FunctionalState LoopbackMode
Definition stm32f4xx_hal_eth.h:257

ETH_MACConfigTypeDef::ExtendedInterPacketGapVal
uint32_t ExtendedInterPacketGapVal
Definition stm32f4xx_hal_eth.h:292

ETH_MACConfigTypeDef::JumboPacket
FunctionalState JumboPacket
Definition stm32f4xx_hal_eth.h:247

ETH_MACConfigTypeDef::InterPacketGapVal
uint32_t InterPacketGapVal
Definition stm32f4xx_hal_eth.h:232

ETH_MACConfigTypeDef::TransmitQueueMode
uint32_t TransmitQueueMode
Definition stm32f4xx_hal_eth.h:322

ETH_MACConfigTypeDef::Support2KPacket
FunctionalState Support2KPacket
Definition stm32f4xx_hal_eth.h:237

ETH_MACConfigTypeDef::BackOffLimit
uint32_t BackOffLimit
Definition stm32f4xx_hal_eth.h:270

ETH_MACConfigTypeDef::ForwardRxErrorPacket
FunctionalState ForwardRxErrorPacket
Definition stm32f4xx_hal_eth.h:330

ETH_MACConfigTypeDef::ChecksumOffload
FunctionalState ChecksumOffload
Definition stm32f4xx_hal_eth.h:230

ETH_MACConfigTypeDef::GiantPacketSizeLimitControl
FunctionalState GiantPacketSizeLimitControl
Definition stm32f4xx_hal_eth.h:235

ETH_MACConfigTypeDef::DeferralCheck
FunctionalState DeferralCheck
Definition stm32f4xx_hal_eth.h:274

ETH_MACConfigTypeDef::ZeroQuantaPause
FunctionalState ZeroQuantaPause
Definition stm32f4xx_hal_eth.h:306

ETH_MACConfigTypeDef::CRCStripTypePacket
FunctionalState CRCStripTypePacket
Definition stm32f4xx_hal_eth.h:239

ETH_MACConfigTypeDef::ReceiveQueueMode
uint32_t ReceiveQueueMode
Definition stm32f4xx_hal_eth.h:325

ETH_MACConfigTypeDef::ForwardRxUndersizedGoodPacket
FunctionalState ForwardRxUndersizedGoodPacket
Definition stm32f4xx_hal_eth.h:332

ETH_MACConfigTypeDef::ProgrammableWatchdog
FunctionalState ProgrammableWatchdog
Definition stm32f4xx_hal_eth.h:295

ETH_MACConfigTypeDef::ReceiveFlowControl
FunctionalState ReceiveFlowControl
Definition stm32f4xx_hal_eth.h:319

ETH_MACConfigTypeDef::CRCCheckingRxPackets
FunctionalState CRCCheckingRxPackets
Definition stm32f4xx_hal_eth.h:282

ETH_MACConfigTypeDef::SourceAddrControl
uint32_t SourceAddrControl
Definition stm32f4xx_hal_eth.h:226

ETH_MACConfigTypeDef::DuplexMode
uint32_t DuplexMode
Definition stm32f4xx_hal_eth.h:254

ETH_MACConfigTypeDef::CarrierSenseDuringTransmit
FunctionalState CarrierSenseDuringTransmit
Definition stm32f4xx_hal_eth.h:265

ETH_MACConfigTypeDef::CarrierSenseBeforeTransmit
FunctionalState CarrierSenseBeforeTransmit
Definition stm32f4xx_hal_eth.h:260

ETH_MACConfigTypeDef::DropTCPIPChecksumErrorPacket
FunctionalState DropTCPIPChecksumErrorPacket
Definition stm32f4xx_hal_eth.h:328

ETH_MACConfigTypeDef::SlowProtocolDetect
FunctionalState SlowProtocolDetect
Definition stm32f4xx_hal_eth.h:280

ETH_MACConfigTypeDef::Watchdog
FunctionalState Watchdog
Definition stm32f4xx_hal_eth.h:243

ETH_MACConfigTypeDef::TransmitFlowControl
FunctionalState TransmitFlowControl
Definition stm32f4xx_hal_eth.h:313

ETH_MACConfigTypeDef::Speed
uint32_t Speed
Definition stm32f4xx_hal_eth.h:251

ETH_MACConfigTypeDef::PauseTime
uint32_t PauseTime
Definition stm32f4xx_hal_eth.h:301

ETH_MACConfigTypeDef::GiantPacketSizeLimit
uint32_t GiantPacketSizeLimit
Definition stm32f4xx_hal_eth.h:285

ETH_MACConfigTypeDef::Jabber
FunctionalState Jabber
Definition stm32f4xx_hal_eth.h:245

ETH_MACFilterConfigTypeDef
ETH MAC filter structure definition.
Definition stm32f4xx_hal_eth.h:620

ETH_MACFilterConfigTypeDef::SrcAddrFiltering
FunctionalState SrcAddrFiltering
Definition stm32f4xx_hal_eth.h:633

ETH_MACFilterConfigTypeDef::BroadcastFilter
FunctionalState BroadcastFilter
Definition stm32f4xx_hal_eth.h:639

ETH_MACFilterConfigTypeDef::ControlPacketsFilter
uint32_t ControlPacketsFilter
Definition stm32f4xx_hal_eth.h:641

ETH_MACFilterConfigTypeDef::SrcAddrInverseFiltering
FunctionalState SrcAddrInverseFiltering
Definition stm32f4xx_hal_eth.h:635

ETH_MACFilterConfigTypeDef::PassAllMulticast
FunctionalState PassAllMulticast
Definition stm32f4xx_hal_eth.h:631

ETH_MACFilterConfigTypeDef::HachOrPerfectFilter
FunctionalState HachOrPerfectFilter
Definition stm32f4xx_hal_eth.h:625

ETH_MACFilterConfigTypeDef::HashUnicast
FunctionalState HashUnicast
Definition stm32f4xx_hal_eth.h:627

ETH_MACFilterConfigTypeDef::ReceiveAllMode
FunctionalState ReceiveAllMode
Definition stm32f4xx_hal_eth.h:623

ETH_MACFilterConfigTypeDef::DestAddrInverseFiltering
FunctionalState DestAddrInverseFiltering
Definition stm32f4xx_hal_eth.h:637

ETH_MACFilterConfigTypeDef::PromiscuousMode
FunctionalState PromiscuousMode
Definition stm32f4xx_hal_eth.h:621

ETH_MACFilterConfigTypeDef::HashMulticast
FunctionalState HashMulticast
Definition stm32f4xx_hal_eth.h:629

ETH_PowerDownConfigTypeDef
ETH Power Down structure definition.
Definition stm32f4xx_hal_eth.h:652

ETH_PowerDownConfigTypeDef::WakeUpPacket
FunctionalState WakeUpPacket
Definition stm32f4xx_hal_eth.h:653

ETH_PowerDownConfigTypeDef::GlobalUnicast
FunctionalState GlobalUnicast
Definition stm32f4xx_hal_eth.h:657

ETH_PowerDownConfigTypeDef::MagicPacket
FunctionalState MagicPacket
Definition stm32f4xx_hal_eth.h:655

ETH_PowerDownConfigTypeDef::WakeUpForward
FunctionalState WakeUpForward
Definition stm32f4xx_hal_eth.h:659

ETH_RxDescListTypeDef
DMA Receive Descriptors Wrapper structure definition.
Definition stm32f4xx_hal_eth.h:191

ETH_RxDescListTypeDef::pRxLastRxDesc
uint32_t pRxLastRxDesc
Definition stm32f4xx_hal_eth.h:207

ETH_RxDescListTypeDef::ItMode
uint32_t ItMode
Definition stm32f4xx_hal_eth.h:194

ETH_RxDescListTypeDef::pRxStart
void * pRxStart
Definition stm32f4xx_hal_eth.h:211

ETH_RxDescListTypeDef::RxDescCnt
uint32_t RxDescCnt
Definition stm32f4xx_hal_eth.h:199

ETH_RxDescListTypeDef::RxDescIdx
uint32_t RxDescIdx
Definition stm32f4xx_hal_eth.h:197

ETH_RxDescListTypeDef::pRxEnd
void * pRxEnd
Definition stm32f4xx_hal_eth.h:213

ETH_RxDescListTypeDef::RxDataLength
uint32_t RxDataLength
Definition stm32f4xx_hal_eth.h:201

ETH_RxDescListTypeDef::TimeStamp
ETH_TimeStampTypeDef TimeStamp
Definition stm32f4xx_hal_eth.h:209

ETH_RxDescListTypeDef::RxBuildDescCnt
uint32_t RxBuildDescCnt
Definition stm32f4xx_hal_eth.h:205

ETH_RxDescListTypeDef::RxBuildDescIdx
uint32_t RxBuildDescIdx
Definition stm32f4xx_hal_eth.h:203

ETH_TimeStampTypeDef
ETH Timestamp structure definition.
Definition stm32f4xx_hal_eth.h:164

ETH_TimeStampTypeDef::TimeStampLow
uint32_t TimeStampLow
Definition stm32f4xx_hal_eth.h:165

ETH_TimeStampTypeDef::TimeStampHigh
uint32_t TimeStampHigh
Definition stm32f4xx_hal_eth.h:166

ETH_TxDescListTypeDef
DMA Transmit Descriptors Wrapper structure definition.
Definition stm32f4xx_hal_eth.h:94

ETH_TxDescListTypeDef::releaseIndex
uint32_t releaseIndex
Definition stm32f4xx_hal_eth.h:105

ETH_TxDescListTypeDef::BuffersInUse
uint32_t BuffersInUse
Definition stm32f4xx_hal_eth.h:103

ETH_TxDescListTypeDef::CurTxDesc
uint32_t CurTxDesc
Definition stm32f4xx_hal_eth.h:97

ETH_TxDescListTypeDef::CurrentPacketAddress
uint32_t * CurrentPacketAddress
Definition stm32f4xx_hal_eth.h:101

ETH_TxPacketConfigTypeDef
Transmit Packet Configuration structure definition.
Definition stm32f4xx_hal_eth.h:115

ETH_TxPacketConfigTypeDef::SrcAddrCtrl
uint32_t SrcAddrCtrl
Definition stm32f4xx_hal_eth.h:123

ETH_TxPacketConfigTypeDef::CRCPadCtrl
uint32_t CRCPadCtrl
Definition stm32f4xx_hal_eth.h:126

ETH_TxPacketConfigTypeDef::PayloadLen
uint32_t PayloadLen
Definition stm32f4xx_hal_eth.h:135

ETH_TxPacketConfigTypeDef::MaxSegmentSize
uint32_t MaxSegmentSize
Definition stm32f4xx_hal_eth.h:132

ETH_TxPacketConfigTypeDef::TxBuffer
ETH_BufferTypeDef * TxBuffer
Definition stm32f4xx_hal_eth.h:121

ETH_TxPacketConfigTypeDef::VlanTag
uint32_t VlanTag
Definition stm32f4xx_hal_eth.h:141

ETH_TxPacketConfigTypeDef::VlanCtrl
uint32_t VlanCtrl
Definition stm32f4xx_hal_eth.h:144

ETH_TxPacketConfigTypeDef::ChecksumCtrl
uint32_t ChecksumCtrl
Definition stm32f4xx_hal_eth.h:129

ETH_TxPacketConfigTypeDef::Length
uint32_t Length
Definition stm32f4xx_hal_eth.h:119

ETH_TxPacketConfigTypeDef::TCPHeaderLen
uint32_t TCPHeaderLen
Definition stm32f4xx_hal_eth.h:138

ETH_TxPacketConfigTypeDef::InnerVlanTag
uint32_t InnerVlanTag
Definition stm32f4xx_hal_eth.h:147

ETH_TxPacketConfigTypeDef::Attributes
uint32_t Attributes
Definition stm32f4xx_hal_eth.h:116

ETH_TxPacketConfigTypeDef::pData
void * pData
Definition stm32f4xx_hal_eth.h:153

ETH_TxPacketConfigTypeDef::InnerVlanCtrl
uint32_t InnerVlanCtrl
Definition stm32f4xx_hal_eth.h:150

__ETH_BufferTypeDef
ETH Buffers List structure definition.
Definition stm32f4xx_hal_eth.h:79

__ETH_BufferTypeDef::buffer
uint8_t * buffer
Definition stm32f4xx_hal_eth.h:80

__ETH_BufferTypeDef::next
struct __ETH_BufferTypeDef * next
Definition stm32f4xx_hal_eth.h:84

__ETH_BufferTypeDef::len
uint32_t len
Definition stm32f4xx_hal_eth.h:82