STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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stm32f4xx_hal_qspi.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32F4xx_HAL_QSPI_H
21#define STM32F4xx_HAL_QSPI_H
22
23#ifdef __cplusplus
24 extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f4xx_hal_def.h"
29
30#if defined(QUADSPI)
31
40/* Exported types ------------------------------------------------------------*/
48typedef struct
49{
50 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
51 This parameter can be a number between 0 and 255 */
52 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
53 This parameter can be a value between 1 and 32 */
54 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
55 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
56 This parameter can be a value of @ref QSPI_SampleShifting */
57 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
58 required to address the flash memory. The flash capacity can be up to 4GB
59 (addressed using 32 bits) in indirect mode, but the addressable space in
60 memory-mapped mode is limited to 256MB
61 This parameter can be a number between 0 and 31 */
62 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
63 of clock cycles which the chip select must remain high between commands.
64 This parameter can be a value of @ref QSPI_ChipSelectHighTime */
65 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
66 This parameter can be a value of @ref QSPI_ClockMode */
67 uint32_t FlashID; /* Specifies the Flash which will be used,
68 This parameter can be a value of @ref QSPI_Flash_Select */
69 uint32_t DualFlash; /* Specifies the Dual Flash Mode State
70 This parameter can be a value of @ref QSPI_DualFlash_Mode */
71}QSPI_InitTypeDef;
72
76typedef enum
77{
78 HAL_QSPI_STATE_RESET = 0x00U,
79 HAL_QSPI_STATE_READY = 0x01U,
80 HAL_QSPI_STATE_BUSY = 0x02U,
81 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U,
82 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U,
83 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,
84 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U,
85 HAL_QSPI_STATE_ABORT = 0x08U,
86 HAL_QSPI_STATE_ERROR = 0x04U
87}HAL_QSPI_StateTypeDef;
88
92#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
93typedef struct __QSPI_HandleTypeDef
94#else
95typedef struct
96#endif
97{
98 QUADSPI_TypeDef *Instance; /* QSPI registers base address */
99 QSPI_InitTypeDef Init; /* QSPI communication parameters */
100 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
101 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
102 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
103 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
104 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
105 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
106 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
107 __IO HAL_LockTypeDef Lock; /* Locking object */
108 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
109 __IO uint32_t ErrorCode; /* QSPI Error code */
110 uint32_t Timeout; /* Timeout for the QSPI memory access */
111#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
112 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi);
113 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
114 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
115 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
116 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
117 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
118 void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
119 void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
120 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi);
121 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi);
122
123 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
124 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
125#endif
126}QSPI_HandleTypeDef;
127
131typedef struct
132{
133 uint32_t Instruction; /* Specifies the Instruction to be sent
134 This parameter can be a value (8-bit) between 0x00 and 0xFF */
135 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
136 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
137 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
138 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
139 uint32_t AddressSize; /* Specifies the Address Size
140 This parameter can be a value of @ref QSPI_AddressSize */
141 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
142 This parameter can be a value of @ref QSPI_AlternateBytesSize */
143 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
144 This parameter can be a number between 0 and 31 */
145 uint32_t InstructionMode; /* Specifies the Instruction Mode
146 This parameter can be a value of @ref QSPI_InstructionMode */
147 uint32_t AddressMode; /* Specifies the Address Mode
148 This parameter can be a value of @ref QSPI_AddressMode */
149 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
150 This parameter can be a value of @ref QSPI_AlternateBytesMode */
151 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
152 This parameter can be a value of @ref QSPI_DataMode */
153 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
154 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
155 until end of memory)*/
156 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
157 This parameter can be a value of @ref QSPI_DdrMode */
158 uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
159 output by one half of system clock in DDR mode.
160 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
161 uint32_t SIOOMode; /* Specifies the send instruction only once mode
162 This parameter can be a value of @ref QSPI_SIOOMode */
163}QSPI_CommandTypeDef;
164
168typedef struct
169{
170 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
171 This parameter can be any value between 0 and 0xFFFFFFFF */
172 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
173 This parameter can be any value between 0 and 0xFFFFFFFF */
174 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
175 This parameter can be any value between 0 and 0xFFFF */
176 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
177 This parameter can be any value between 1 and 4 */
178 uint32_t MatchMode; /* Specifies the method used for determining a match.
179 This parameter can be a value of @ref QSPI_MatchMode */
180 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
181 This parameter can be a value of @ref QSPI_AutomaticStop */
182}QSPI_AutoPollingTypeDef;
183
187typedef struct
188{
189 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
190 This parameter can be any value between 0 and 0xFFFF */
191 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
192 This parameter can be a value of @ref QSPI_TimeOutActivation */
193}QSPI_MemoryMappedTypeDef;
194
195#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
199typedef enum
200{
201 HAL_QSPI_ERROR_CB_ID = 0x00U,
202 HAL_QSPI_ABORT_CB_ID = 0x01U,
203 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U,
204 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U,
205 HAL_QSPI_RX_CPLT_CB_ID = 0x04U,
206 HAL_QSPI_TX_CPLT_CB_ID = 0x05U,
207 HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U,
208 HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U,
209 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U,
210 HAL_QSPI_TIMEOUT_CB_ID = 0x09U,
212 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU,
213 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0
214}HAL_QSPI_CallbackIDTypeDef;
215
219typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
220#endif
225/* Exported constants --------------------------------------------------------*/
233#define HAL_QSPI_ERROR_NONE 0x00000000U
234#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U
235#define HAL_QSPI_ERROR_TRANSFER 0x00000002U
236#define HAL_QSPI_ERROR_DMA 0x00000004U
237#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U
238#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
239#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U
240#endif
248#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U
249#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT)
257#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U
258#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0)
259#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1)
260#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
261#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2)
262#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
263#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
264#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT)
272#define QSPI_CLOCK_MODE_0 0x00000000U
273#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE)
281#define QSPI_FLASH_ID_1 0x00000000U
282#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
290#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
291#define QSPI_DUALFLASH_DISABLE 0x00000000U
299#define QSPI_ADDRESS_8_BITS 0x00000000U
300#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0)
301#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1)
302#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE)
310#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U
311#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0)
312#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1)
313#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE)
321#define QSPI_INSTRUCTION_NONE 0x00000000U
322#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0)
323#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1)
324#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE)
332#define QSPI_ADDRESS_NONE 0x00000000U
333#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0)
334#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1)
335#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE)
343#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U
344#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0)
345#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1)
346#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE)
354#define QSPI_DATA_NONE 0x00000000U
355#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0)
356#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1)
357#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE)
365#define QSPI_DDR_MODE_DISABLE 0x00000000U
366#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM)
374#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U
375#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC)
383#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U
384#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO)
392#define QSPI_MATCH_MODE_AND 0x00000000U
393#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM)
401#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U
402#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS)
410#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U
411#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN)
419#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY
420#define QSPI_FLAG_TO QUADSPI_SR_TOF
421#define QSPI_FLAG_SM QUADSPI_SR_SMF
422#define QSPI_FLAG_FT QUADSPI_SR_FTF
423#define QSPI_FLAG_TC QUADSPI_SR_TCF
424#define QSPI_FLAG_TE QUADSPI_SR_TEF
432#define QSPI_IT_TO QUADSPI_CR_TOIE
433#define QSPI_IT_SM QUADSPI_CR_SMIE
434#define QSPI_IT_FT QUADSPI_CR_FTIE
435#define QSPI_IT_TC QUADSPI_CR_TCIE
436#define QSPI_IT_TE QUADSPI_CR_TEIE
445#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
454/* Exported macros -----------------------------------------------------------*/
462#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
463#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
464 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
465 (__HANDLE__)->MspInitCallback = NULL; \
466 (__HANDLE__)->MspDeInitCallback = NULL; \
467 } while(0)
468#else
469#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
470#endif
471
476#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
477
482#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
483
495#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
496
497
509#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
510
522#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
523
537#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
538
549#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
554/* Exported functions --------------------------------------------------------*/
562/* Initialization/de-initialization functions ********************************/
563HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
564HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
565void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
566void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
574/* IO operation functions *****************************************************/
575/* QSPI IRQ handler method */
576void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
577
578/* QSPI indirect mode */
579HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
580HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
581HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
582HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
583HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
584HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
585HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
586HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
587
588/* QSPI status flag polling mode */
589HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
590HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
591
592/* QSPI memory-mapped mode */
593HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
594
595/* Callback functions in non-blocking modes ***********************************/
596void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
597void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
598void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
599
600/* QSPI indirect mode */
601void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
602void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
603void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
604void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
605void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
606
607/* QSPI status flag polling mode */
608void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
609
610/* QSPI memory-mapped mode */
611void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
612
613#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
614/* QSPI callback registering/unregistering */
615HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
616HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
617#endif
625/* Peripheral Control and State functions ************************************/
626HAL_QSPI_StateTypeDef HAL_QSPI_GetState (const QSPI_HandleTypeDef *hqspi);
627uint32_t HAL_QSPI_GetError (const QSPI_HandleTypeDef *hqspi);
628HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
629HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
630void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
631HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
632uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi);
633HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
641/* End of exported functions -------------------------------------------------*/
642
643/* Private macros ------------------------------------------------------------*/
647#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
648
649#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
650
651#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
652 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
653
654#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
655
656#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
657 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
658 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
659 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
660 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
661 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
662 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
663 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
664
665#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
666 ((CLKMODE) == QSPI_CLOCK_MODE_3))
667
668#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
669 ((FLASH_ID) == QSPI_FLASH_ID_2))
670
671#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
672 ((MODE) == QSPI_DUALFLASH_DISABLE))
673
674#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
675
676#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
677 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
678 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
679 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
680
681#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
682 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
683 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
684 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
685
686#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
687
688#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
689 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
690 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
691 ((MODE) == QSPI_INSTRUCTION_4_LINES))
692
693#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
694 ((MODE) == QSPI_ADDRESS_1_LINE) || \
695 ((MODE) == QSPI_ADDRESS_2_LINES) || \
696 ((MODE) == QSPI_ADDRESS_4_LINES))
697
698#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
699 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
700 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
701 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
702
703#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
704 ((MODE) == QSPI_DATA_1_LINE) || \
705 ((MODE) == QSPI_DATA_2_LINES) || \
706 ((MODE) == QSPI_DATA_4_LINES))
707
708#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
709 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
710
711#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
712 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
713
714#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
715 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
716
717#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
718
719#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
720
721#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
722 ((MODE) == QSPI_MATCH_MODE_OR))
723
724#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
725 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
726
727#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
728 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
729
730#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
734/* End of private macros -----------------------------------------------------*/
735
744#endif /* defined(QUADSPI) */
745
746#ifdef __cplusplus
747}
748#endif
749
750#endif /* STM32F4xx_HAL_QSPI_H */
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition stm32f4xx_hal_def.h:39
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition stm32f4xx_hal_def.h:50
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition stm32f4xx_hal_dma.h:139