20#ifndef STM32F4xx_HAL_SDRAM_H
21#define STM32F4xx_HAL_SDRAM_H
27#if defined(FMC_Bank5_6)
30#include "stm32f4xx_ll_fmc.h"
51 HAL_SDRAM_STATE_RESET = 0x00U,
52 HAL_SDRAM_STATE_READY = 0x01U,
53 HAL_SDRAM_STATE_BUSY = 0x02U,
54 HAL_SDRAM_STATE_ERROR = 0x03U,
55 HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U,
56 HAL_SDRAM_STATE_PRECHARGED = 0x05U
58} HAL_SDRAM_StateTypeDef;
63#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
64typedef struct __SDRAM_HandleTypeDef
69 FMC_SDRAM_TypeDef *Instance;
71 FMC_SDRAM_InitTypeDef Init;
73 __IO HAL_SDRAM_StateTypeDef State;
79#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
80 void (* MspInitCallback)(
struct __SDRAM_HandleTypeDef *hsdram);
81 void (* MspDeInitCallback)(
struct __SDRAM_HandleTypeDef *hsdram);
82 void (* RefreshErrorCallback)(
struct __SDRAM_HandleTypeDef *hsdram);
88#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
94 HAL_SDRAM_MSP_INIT_CB_ID = 0x00U,
95 HAL_SDRAM_MSP_DEINIT_CB_ID = 0x01U,
96 HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U,
97 HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U,
98 HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U
99} HAL_SDRAM_CallbackIDTypeDef;
104typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram);
122#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
123#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
124 (__HANDLE__)->State = HAL_SDRAM_STATE_RESET; \
125 (__HANDLE__)->MspInitCallback = NULL; \
126 (__HANDLE__)->MspDeInitCallback = NULL; \
129#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
146HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
148void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
149void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
151void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
152void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
164HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
165 uint32_t BufferSize);
166HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
167 uint32_t BufferSize);
168HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
169 uint32_t BufferSize);
170HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
171 uint32_t BufferSize);
172HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
173 uint32_t BufferSize);
174HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
175 uint32_t BufferSize);
177HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
178 uint32_t BufferSize);
179HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
180 uint32_t BufferSize);
182#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
184HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
185 pSDRAM_CallbackTypeDef pCallback);
186HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId);
187HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
188 pSDRAM_DmaCallbackTypeDef pCallback);
201HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
203HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
204HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
205uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
215HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
HAL_StatusTypeDef
HAL Status structures definition
HAL_LockTypeDef
HAL Lock structures definition
DMA handle Structure definition.