STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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stm32f4xx_hal_spdifrx.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32F4xx_HAL_SPDIFRX_H
21#define STM32F4xx_HAL_SPDIFRX_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f4xx_hal_def.h"
29
30#if defined(STM32F446xx)
34#if defined (SPDIFRX)
35
40/* Exported types ------------------------------------------------------------*/
48typedef struct
49{
50 uint32_t InputSelection;
53 uint32_t Retries;
56 uint32_t WaitForActivity;
59 uint32_t ChannelSelection;
63 uint32_t DataFormat;
66 uint32_t StereoMode;
69 uint32_t PreambleTypeMask;
73 uint32_t ChannelStatusMask;
77 uint32_t ValidityBitMask;
80 uint32_t ParityErrorMask;
83} SPDIFRX_InitTypeDef;
84
88typedef struct
89{
90 uint32_t DataFormat;
93 uint32_t StereoMode;
96 uint32_t PreambleTypeMask;
100 uint32_t ChannelStatusMask;
104 uint32_t ValidityBitMask;
107 uint32_t ParityErrorMask;
111} SPDIFRX_SetDataFormatTypeDef;
112
116typedef enum
117{
118 HAL_SPDIFRX_STATE_RESET = 0x00U,
119 HAL_SPDIFRX_STATE_READY = 0x01U,
120 HAL_SPDIFRX_STATE_BUSY = 0x02U,
121 HAL_SPDIFRX_STATE_BUSY_RX = 0x03U,
122 HAL_SPDIFRX_STATE_BUSY_CX = 0x04U,
123 HAL_SPDIFRX_STATE_ERROR = 0x07U
124} HAL_SPDIFRX_StateTypeDef;
125
129#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
130typedef struct __SPDIFRX_HandleTypeDef
131#else
132typedef struct
133#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
134{
135 SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */
136
137 SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */
138
139 uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */
140
141 uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */
142
143 __IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */
144
145 __IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter
146 (This field is initialized at the
147 same value as transfer size at the
148 beginning of the transfer and
149 decremented when a sample is received.
150 NbSamplesReceived = RxBufferSize-RxBufferCount) */
151
152 __IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */
153
154 __IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter
155 (This field is initialized at the
156 same value as transfer size at the
157 beginning of the transfer and
158 decremented when a sample is received.
159 NbSamplesReceived = RxBufferSize-RxBufferCount) */
160
161 DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information
162 DMA handle parameters */
163
164 DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */
165
166 __IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */
167
168 __IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */
169
170 __IO uint32_t ErrorCode; /* SPDIFRX Error code */
171
172#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
173 void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);
175 void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);
176 void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);
178 void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);
179 void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);
180 void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);
181 void (* MspDeInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);
182#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
183
184} SPDIFRX_HandleTypeDef;
185
186#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
190typedef enum
191{
192 HAL_SPDIFRX_RX_HALF_CB_ID = 0x00U,
193 HAL_SPDIFRX_RX_CPLT_CB_ID = 0x01U,
194 HAL_SPDIFRX_CX_HALF_CB_ID = 0x02U,
195 HAL_SPDIFRX_CX_CPLT_CB_ID = 0x03U,
196 HAL_SPDIFRX_ERROR_CB_ID = 0x04U,
197 HAL_SPDIFRX_MSPINIT_CB_ID = 0x05U,
198 HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U
199} HAL_SPDIFRX_CallbackIDTypeDef;
200
204typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif);
206#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
210/* Exported constants --------------------------------------------------------*/
217#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U)
218#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U)
219#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U)
220#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U)
221#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U)
222#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U)
223#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
224#define HAL_SPDIFRX_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)
225#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
233#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U)
234#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U)
235#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U)
236#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U)
244#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U)
245#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U)
246#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U)
247#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U)
255#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U)
256#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
264#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U)
265#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
273#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied
274 into the SPDIF_DR */
275#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied
276 into the SPDIF_DR, zeros are written instead*/
284#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)
285#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
293#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U)
294#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
302#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U)
303#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
311#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U)
312#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U)
313#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U)
321#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U)
322#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
331#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU)
332#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U)
333#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
341#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
342#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
343#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
344#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
345#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
346#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
347#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
355#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
356#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
357#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
358#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
359#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
360#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
361#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
362#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
363#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
372/* Exported macros -----------------------------------------------------------*/
381#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
382#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\
383 (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\
384 (__HANDLE__)->MspInitCallback = NULL;\
385 (__HANDLE__)->MspDeInitCallback = NULL;\
386 }while(0)
387#else
388#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET)
389#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
390
395#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
396
401#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
402
403
408#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
409
410
424#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
425#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR\
426 &= (uint16_t)(~(__INTERRUPT__)))
427
441#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\
442 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
443
459#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\
460 & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
461
473#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
474
479/* Exported functions --------------------------------------------------------*/
487/* Initialization/de-initialization functions **********************************/
488HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
489HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif);
490void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
491void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
492HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat);
493
494/* Callbacks Register/UnRegister functions ***********************************/
495#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
496HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID,
497 pSPDIFRX_CallbackTypeDef pCallback);
498HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif,
499 HAL_SPDIFRX_CallbackIDTypeDef CallbackID);
500#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
508/* I/O operation functions ***************************************************/
509/* Blocking mode: Polling */
510HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
511 uint32_t Timeout);
512HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
513 uint32_t Timeout);
514
515/* Non-Blocking mode: Interrupt */
516HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
517HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
518void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
519
520/* Non-Blocking mode: DMA */
521HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
522HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
523HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
524
525/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
526void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
527void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
528void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);
529void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
530void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
538/* Peripheral Control and State functions ************************************/
539HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif);
540uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif);
548/* Private types -------------------------------------------------------------*/
549/* Private variables ---------------------------------------------------------*/
550/* Private constants ---------------------------------------------------------*/
551/* Private macros ------------------------------------------------------------*/
555#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \
556 ((INPUT) == SPDIFRX_INPUT_IN2) || \
557 ((INPUT) == SPDIFRX_INPUT_IN3) || \
558 ((INPUT) == SPDIFRX_INPUT_IN0))
559
560#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
561 ((RET) == SPDIFRX_MAXRETRIES_3) || \
562 ((RET) == SPDIFRX_MAXRETRIES_15) || \
563 ((RET) == SPDIFRX_MAXRETRIES_63))
564
565#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
566 ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
567
568#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
569 ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
570
571#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
572 ((VAL) == SPDIFRX_VALIDITYMASK_ON))
573
574#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
575 ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
576
577#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
578 ((CHANNEL) == SPDIFRX_CHANNEL_B))
579
580#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
581 ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
582 ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
583
584#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
585 ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
586
587#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
588 ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
589
594/* Private functions ---------------------------------------------------------*/
605#endif /* SPDIFRX */
609#endif /* STM32F446xx */
610
611#ifdef __cplusplus
612}
613#endif
614
615
616#endif /* STM32F4xx_HAL_SPDIFRX_H */
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition stm32f4xx_hal_def.h:39
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition stm32f4xx_hal_def.h:50
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition stm32f4xx_hal_dma.h:139