STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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stm32f4xx_hal_spi.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32F4xx_HAL_SPI_H
21#define STM32F4xx_HAL_SPI_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f4xx_hal_def.h"
29
38/* Exported types ------------------------------------------------------------*/
46typedef struct
47{
48 uint32_t Mode;
51 uint32_t Direction;
54 uint32_t DataSize;
57 uint32_t CLKPolarity;
60 uint32_t CLKPhase;
63 uint32_t NSS;
73 uint32_t FirstBit;
76 uint32_t TIMode;
79 uint32_t CRCCalculation;
82 uint32_t CRCPolynomial;
85
100
105{
106 SPI_TypeDef *Instance;
110 const uint8_t *pTxBuffPtr;
112 uint16_t TxXferSize;
114 __IO uint16_t TxXferCount;
116 uint8_t *pRxBuffPtr;
118 uint16_t RxXferSize;
120 __IO uint16_t RxXferCount;
122 void (*RxISR)(struct __SPI_HandleTypeDef *hspi);
124 void (*TxISR)(struct __SPI_HandleTypeDef *hspi);
134 __IO uint32_t ErrorCode;
136#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
137 void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);
138 void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);
139 void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);
140 void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);
141 void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);
142 void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);
143 void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);
144 void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);
145 void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);
146 void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);
148#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
150
151#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
155typedef enum
156{
157 HAL_SPI_TX_COMPLETE_CB_ID = 0x00U,
158 HAL_SPI_RX_COMPLETE_CB_ID = 0x01U,
159 HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U,
160 HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U,
161 HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U,
162 HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U,
163 HAL_SPI_ERROR_CB_ID = 0x06U,
164 HAL_SPI_ABORT_CB_ID = 0x07U,
165 HAL_SPI_MSPINIT_CB_ID = 0x08U,
166 HAL_SPI_MSPDEINIT_CB_ID = 0x09U
168} HAL_SPI_CallbackIDTypeDef;
169
173typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi);
175#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
180/* Exported constants --------------------------------------------------------*/
188#define HAL_SPI_ERROR_NONE (0x00000000U)
189#define HAL_SPI_ERROR_MODF (0x00000001U)
190#define HAL_SPI_ERROR_CRC (0x00000002U)
191#define HAL_SPI_ERROR_OVR (0x00000004U)
192#define HAL_SPI_ERROR_FRE (0x00000008U)
193#define HAL_SPI_ERROR_DMA (0x00000010U)
194#define HAL_SPI_ERROR_FLAG (0x00000020U)
195#define HAL_SPI_ERROR_ABORT (0x00000040U)
196#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
197#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U)
198#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
206#define SPI_MODE_SLAVE (0x00000000U)
207#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
215#define SPI_DIRECTION_2LINES (0x00000000U)
216#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
217#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
225#define SPI_DATASIZE_8BIT (0x00000000U)
226#define SPI_DATASIZE_16BIT SPI_CR1_DFF
234#define SPI_POLARITY_LOW (0x00000000U)
235#define SPI_POLARITY_HIGH SPI_CR1_CPOL
243#define SPI_PHASE_1EDGE (0x00000000U)
244#define SPI_PHASE_2EDGE SPI_CR1_CPHA
252#define SPI_NSS_SOFT SPI_CR1_SSM
253#define SPI_NSS_HARD_INPUT (0x00000000U)
254#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
262#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
263#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
264#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
265#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
266#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
267#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
268#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
269#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
277#define SPI_FIRSTBIT_MSB (0x00000000U)
278#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
286#define SPI_TIMODE_DISABLE (0x00000000U)
287#define SPI_TIMODE_ENABLE SPI_CR2_FRF
295#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
296#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
304#define SPI_IT_TXE SPI_CR2_TXEIE
305#define SPI_IT_RXNE SPI_CR2_RXNEIE
306#define SPI_IT_ERR SPI_CR2_ERRIE
314#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
315#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
316#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
317#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
318#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
319#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
320#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
321#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
322 | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)
331/* Exported macros -----------------------------------------------------------*/
341#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
342#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
343 (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
344 (__HANDLE__)->MspInitCallback = NULL; \
345 (__HANDLE__)->MspDeInitCallback = NULL; \
346 } while(0)
347#else
348#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
349#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
350
361#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
362
373#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
374
385#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
386 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
387
402#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
403
409#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
410
416#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
417 do{ \
418 __IO uint32_t tmpreg_modf = 0x00U; \
419 tmpreg_modf = (__HANDLE__)->Instance->SR; \
420 CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
421 UNUSED(tmpreg_modf); \
422 } while(0U)
423
429#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
430 do{ \
431 __IO uint32_t tmpreg_ovr = 0x00U; \
432 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
433 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
434 UNUSED(tmpreg_ovr); \
435 } while(0U)
436
442#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
443 do{ \
444 __IO uint32_t tmpreg_fre = 0x00U; \
445 tmpreg_fre = (__HANDLE__)->Instance->SR; \
446 UNUSED(tmpreg_fre); \
447 }while(0U)
448
454#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
455
461#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
462
467/* Private macros ------------------------------------------------------------*/
477#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
478
484#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
485
491#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
492 SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
493
507#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
508 ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
509
519#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
520 (__INTERRUPT__)) ? SET : RESET)
521
527#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
528 ((__MODE__) == SPI_MODE_MASTER))
529
535#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
536 ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
537 ((__MODE__) == SPI_DIRECTION_1LINE))
538
543#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
544
549#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
550 ((__MODE__) == SPI_DIRECTION_1LINE))
551
557#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
558 ((__DATASIZE__) == SPI_DATASIZE_8BIT))
559
565#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
566 ((__CPOL__) == SPI_POLARITY_HIGH))
567
573#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
574 ((__CPHA__) == SPI_PHASE_2EDGE))
575
581#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
582 ((__NSS__) == SPI_NSS_HARD_INPUT) || \
583 ((__NSS__) == SPI_NSS_HARD_OUTPUT))
584
590#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
591 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
592 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
593 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
594 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
595 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
596 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
597 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
598
604#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
605 ((__BIT__) == SPI_FIRSTBIT_LSB))
606
612#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
613 ((__MODE__) == SPI_TIMODE_ENABLE))
614
620#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
621 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
622
628#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
629 ((__POLYNOMIAL__) <= 0xFFFFU) && \
630 (((__POLYNOMIAL__)&0x1U) != 0U))
631
636#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
637
642/* Exported functions --------------------------------------------------------*/
650/* Initialization/de-initialization functions ********************************/
655
656/* Callbacks Register/UnRegister functions ***********************************/
657#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
658HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
659 pSPI_CallbackTypeDef pCallback);
660HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
661#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
669/* I/O operation functions ***************************************************/
670HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
671HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
672HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
673 uint16_t Size, uint32_t Timeout);
674HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
675HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
676HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
677 uint16_t Size);
678HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
679HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
680HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
681 uint16_t Size);
685/* Transfer Abort functions */
688
705/* Peripheral State and Error functions ***************************************/
707uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
724#ifdef __cplusplus
725}
726#endif
727
728#endif /* STM32F4xx_HAL_SPI_H */
729
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the as...
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
De-Initialize the SPI peripheral.
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
SPI error callback.
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi)
Return the SPI error code.
HAL_SPI_StateTypeDef
HAL SPI State structure definition.
struct __SPI_HandleTypeDef SPI_HandleTypeDef
SPI handle Structure definition.
@ HAL_SPI_STATE_BUSY
@ HAL_SPI_STATE_ABORT
@ HAL_SPI_STATE_ERROR
@ HAL_SPI_STATE_BUSY_TX
@ HAL_SPI_STATE_BUSY_TX_RX
@ HAL_SPI_STATE_READY
@ HAL_SPI_STATE_RESET
@ HAL_SPI_STATE_BUSY_RX
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition
HAL_LockTypeDef
HAL Lock structures definition
SPI Configuration Structure definition.
DMA handle Structure definition.
SPI handle Structure definition.
DMA_HandleTypeDef * hdmarx
void(* TxISR)(struct __SPI_HandleTypeDef *hspi)
void(* RxISR)(struct __SPI_HandleTypeDef *hspi)
DMA_HandleTypeDef * hdmatx
__IO HAL_SPI_StateTypeDef State
const uint8_t * pTxBuffPtr