Collaboration diagram for ETH DMA Rx Descriptor Bit Definition:

Macros
#define	ETH_DMARXDESC_OWN 0x80000000U
	Bit definition of RDES0 register: DMA Rx descriptor status register.

#define	ETH_DMARXDESC_AFM 0x40000000U

#define	ETH_DMARXDESC_FL 0x3FFF0000U

#define	ETH_DMARXDESC_ES 0x00008000U

#define	ETH_DMARXDESC_DE 0x00004000U

#define	ETH_DMARXDESC_SAF 0x00002000U

#define	ETH_DMARXDESC_LE 0x00001000U

#define	ETH_DMARXDESC_OE 0x00000800U

#define	ETH_DMARXDESC_VLAN 0x00000400U

#define	ETH_DMARXDESC_FS 0x00000200U

#define	ETH_DMARXDESC_LS 0x00000100U

#define	ETH_DMARXDESC_IPV4HCE 0x00000080U

#define	ETH_DMARXDESC_LC 0x00000040U

#define	ETH_DMARXDESC_FT 0x00000020U

#define	ETH_DMARXDESC_RWT 0x00000010U

#define	ETH_DMARXDESC_RE 0x00000008U

#define	ETH_DMARXDESC_DBE 0x00000004U

#define	ETH_DMARXDESC_CE 0x00000002U

#define	ETH_DMARXDESC_MAMPCE 0x00000001U

#define	ETH_DMARXDESC_DIC 0x80000000U
	Bit definition of RDES1 register.

#define	ETH_DMARXDESC_RBS2 0x1FFF0000U

#define	ETH_DMARXDESC_RER 0x00008000U

#define	ETH_DMARXDESC_RCH 0x00004000U

#define	ETH_DMARXDESC_RBS1 0x00001FFFU

#define	ETH_DMARXDESC_B1AP 0xFFFFFFFFU
	Bit definition of RDES2 register.

#define	ETH_DMARXDESC_B2AP 0xFFFFFFFFU
	Bit definition of RDES3 register.

#define	ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */

#define	ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */

#define	ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */

#define	ETH_DMAPTPRXDESC_PTPMT_SYNC

#define	ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP

#define	ETH_DMAPTPRXDESC_PTPMT_DELAYREQ

#define	ETH_DMAPTPRXDESC_PTPMT_DELAYRESP

#define	ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE

#define	ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG

#define	ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL

#define	ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */

#define	ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */

#define	ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */

#define	ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */

#define	ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */

#define	ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */

#define	ETH_DMAPTPRXDESC_IPPT_UDP

#define	ETH_DMAPTPRXDESC_IPPT_TCP

#define	ETH_DMAPTPRXDESC_IPPT_ICMP

#define	ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */

#define	ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */

Detailed Description

Macro Definition Documentation

◆ ETH_DMARXDESC_OWN

#define ETH_DMARXDESC_OWN 0x80000000U

#include <stm32f4xx_hal_eth.h>

Bit definition of RDES0 register: DMA Rx descriptor status register.

OWN bit: descriptor is owned by DMA engine

Definition at line 777 of file stm32f4xx_hal_eth.h.

Referenced by ETH_DMARxDescListInit(), ETH_UpdateDescriptor(), and HAL_ETH_ReadData().

◆ ETH_DMARXDESC_AFM

#define ETH_DMARXDESC_AFM 0x40000000U

#include <stm32f4xx_hal_eth.h>

DA Filter Fail for the rx frame

Definition at line 778 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_FL

#define ETH_DMARXDESC_FL 0x3FFF0000U

#include <stm32f4xx_hal_eth.h>

Receive descriptor frame length

Definition at line 779 of file stm32f4xx_hal_eth.h.

Referenced by HAL_ETH_ReadData().

◆ ETH_DMARXDESC_ES

#define ETH_DMARXDESC_ES 0x00008000U

#include <stm32f4xx_hal_eth.h>

Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE

Definition at line 780 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_DE

#define ETH_DMARXDESC_DE 0x00004000U

#include <stm32f4xx_hal_eth.h>

Descriptor error: no more descriptors for receive frame

Definition at line 781 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_SAF

#define ETH_DMARXDESC_SAF 0x00002000U

#include <stm32f4xx_hal_eth.h>

SA Filter Fail for the received frame

Definition at line 782 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_LE

#define ETH_DMARXDESC_LE 0x00001000U

#include <stm32f4xx_hal_eth.h>

Frame size not matching with length field

Definition at line 783 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_OE

#define ETH_DMARXDESC_OE 0x00000800U

#include <stm32f4xx_hal_eth.h>

Overflow Error: Frame was damaged due to buffer overflow

Definition at line 784 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_VLAN

#define ETH_DMARXDESC_VLAN 0x00000400U

#include <stm32f4xx_hal_eth.h>

VLAN Tag: received frame is a VLAN frame

Definition at line 785 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_FS

#define ETH_DMARXDESC_FS 0x00000200U

#include <stm32f4xx_hal_eth.h>

First descriptor of the frame

Definition at line 786 of file stm32f4xx_hal_eth.h.

Referenced by HAL_ETH_ReadData().

◆ ETH_DMARXDESC_LS

#define ETH_DMARXDESC_LS 0x00000100U

#include <stm32f4xx_hal_eth.h>

Last descriptor of the frame

Definition at line 787 of file stm32f4xx_hal_eth.h.

Referenced by HAL_ETH_ReadData().

◆ ETH_DMARXDESC_IPV4HCE

#define ETH_DMARXDESC_IPV4HCE 0x00000080U

#include <stm32f4xx_hal_eth.h>

IPC Checksum Error: Rx Ipv4 header checksum error

Definition at line 788 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_LC

#define ETH_DMARXDESC_LC 0x00000040U

#include <stm32f4xx_hal_eth.h>

Late collision occurred during reception

Definition at line 789 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_FT

#define ETH_DMARXDESC_FT 0x00000020U

#include <stm32f4xx_hal_eth.h>

Frame type - Ethernet, otherwise 802.3

Definition at line 790 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_RWT

#define ETH_DMARXDESC_RWT 0x00000010U

#include <stm32f4xx_hal_eth.h>

Receive Watchdog Timeout: watchdog timer expired during reception

Definition at line 791 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_RE

#define ETH_DMARXDESC_RE 0x00000008U

#include <stm32f4xx_hal_eth.h>

Receive error: error reported by MII interface

Definition at line 792 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_DBE

#define ETH_DMARXDESC_DBE 0x00000004U

#include <stm32f4xx_hal_eth.h>

Dribble bit error: frame contains non int multiple of 8 bits

Definition at line 793 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_CE

#define ETH_DMARXDESC_CE 0x00000002U

#include <stm32f4xx_hal_eth.h>

CRC error

Definition at line 794 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_MAMPCE

#define ETH_DMARXDESC_MAMPCE 0x00000001U

#include <stm32f4xx_hal_eth.h>

Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error

Definition at line 795 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_DIC

#define ETH_DMARXDESC_DIC 0x80000000U

#include <stm32f4xx_hal_eth.h>

Bit definition of RDES1 register.

Disable Interrupt on Completion

Definition at line 800 of file stm32f4xx_hal_eth.h.

Referenced by ETH_UpdateDescriptor(), and HAL_ETH_Stop_IT().

◆ ETH_DMARXDESC_RBS2

#define ETH_DMARXDESC_RBS2 0x1FFF0000U

#include <stm32f4xx_hal_eth.h>

Receive Buffer2 Size

Definition at line 801 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_RER

#define ETH_DMARXDESC_RER 0x00008000U

#include <stm32f4xx_hal_eth.h>

Receive End of Ring

Definition at line 802 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_RCH

#define ETH_DMARXDESC_RCH 0x00004000U

#include <stm32f4xx_hal_eth.h>

Second Address Chained

Definition at line 803 of file stm32f4xx_hal_eth.h.

Referenced by ETH_DMARxDescListInit(), and ETH_UpdateDescriptor().

◆ ETH_DMARXDESC_RBS1

#define ETH_DMARXDESC_RBS1 0x00001FFFU

#include <stm32f4xx_hal_eth.h>

Receive Buffer1 Size

Definition at line 804 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_B1AP

#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU

#include <stm32f4xx_hal_eth.h>

Bit definition of RDES2 register.

Buffer1 Address Pointer

Definition at line 809 of file stm32f4xx_hal_eth.h.

◆ ETH_DMARXDESC_B2AP

#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU

#include <stm32f4xx_hal_eth.h>

Bit definition of RDES3 register.

Buffer2 Address Pointer

Definition at line 814 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_PTPV

#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */

#include <stm32f4xx_hal_eth.h>

Definition at line 827 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_PTPFT

#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */

#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE

#include <stm32f4xx_hal_eth.h>

Value:

                                                                                   0x00000500U  /* PdelayReq message
                                                                                   (peer-to-peer transparent clock)
                                                                                    or Announce message (Ordinary
                                                                                    or Boundary clock) */

Definition at line 834 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG

#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG

#include <stm32f4xx_hal_eth.h>

Value:

                                                                                   0x00000600U  /* PdelayResp message
                                                                                   (peer-to-peer transparent clock)
                                                                                    or Management message (Ordinary
                                                                                    or Boundary clock)  */

Definition at line 835 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL

#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL

#include <stm32f4xx_hal_eth.h>

Value:

                                                                                  0x00000700U  /* PdelayRespFollowUp message
                                                                                  (peer-to-peer transparent clock)
                                                                                   or Signaling message (Ordinary
                                                                                   or Boundary clock) */

Definition at line 836 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_IPV6PR

#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */

#include <stm32f4xx_hal_eth.h>

Definition at line 837 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_IPV4PR

#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */

#include <stm32f4xx_hal_eth.h>

Definition at line 838 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_IPCB

#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */

#include <stm32f4xx_hal_eth.h>

Definition at line 839 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_IPPE

#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */

#include <stm32f4xx_hal_eth.h>

Definition at line 840 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_IPHE

#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */

#include <stm32f4xx_hal_eth.h>

Definition at line 841 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_IPPT

#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */

#include <stm32f4xx_hal_eth.h>

Definition at line 842 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_IPPT_UDP

#define ETH_DMAPTPRXDESC_IPPT_UDP

#include <stm32f4xx_hal_eth.h>

Value:

0x00000001U /* UDP payload encapsulated in

the IP datagram */

Definition at line 843 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_IPPT_TCP

#define ETH_DMAPTPRXDESC_IPPT_TCP

#include <stm32f4xx_hal_eth.h>

Value:

0x00000002U /* TCP payload encapsulated in

the IP datagram */

Definition at line 844 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_IPPT_ICMP

#define ETH_DMAPTPRXDESC_IPPT_ICMP

#include <stm32f4xx_hal_eth.h>

Value:

0x00000003U /* ICMP payload encapsulated in

the IP datagram */

Definition at line 845 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_RTSL

#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */

#include <stm32f4xx_hal_eth.h>

Definition at line 848 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPRXDESC_RTSH

#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */

#include <stm32f4xx_hal_eth.h>

Definition at line 851 of file stm32f4xx_hal_eth.h.

Macros

Detailed Description

Macro Definition Documentation

◆ ETH_DMARXDESC_OWN

◆ ETH_DMARXDESC_AFM

◆ ETH_DMARXDESC_FL

◆ ETH_DMARXDESC_ES

◆ ETH_DMARXDESC_DE

◆ ETH_DMARXDESC_SAF

◆ ETH_DMARXDESC_LE

◆ ETH_DMARXDESC_OE

◆ ETH_DMARXDESC_VLAN

◆ ETH_DMARXDESC_FS

◆ ETH_DMARXDESC_LS

◆ ETH_DMARXDESC_IPV4HCE

◆ ETH_DMARXDESC_LC

◆ ETH_DMARXDESC_FT

◆ ETH_DMARXDESC_RWT

◆ ETH_DMARXDESC_RE

◆ ETH_DMARXDESC_DBE

◆ ETH_DMARXDESC_CE

◆ ETH_DMARXDESC_MAMPCE

◆ ETH_DMARXDESC_DIC

◆ ETH_DMARXDESC_RBS2

◆ ETH_DMARXDESC_RER

◆ ETH_DMARXDESC_RCH

◆ ETH_DMARXDESC_RBS1

◆ ETH_DMARXDESC_B1AP

◆ ETH_DMARXDESC_B2AP

◆ ETH_DMAPTPRXDESC_PTPV

◆ ETH_DMAPTPRXDESC_PTPFT

◆ ETH_DMAPTPRXDESC_PTPMT

◆ ETH_DMAPTPRXDESC_PTPMT_SYNC

◆ ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP

◆ ETH_DMAPTPRXDESC_PTPMT_DELAYREQ

◆ ETH_DMAPTPRXDESC_PTPMT_DELAYRESP

◆ ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE

◆ ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG

◆ ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL

◆ ETH_DMAPTPRXDESC_IPV6PR

◆ ETH_DMAPTPRXDESC_IPV4PR

◆ ETH_DMAPTPRXDESC_IPCB

◆ ETH_DMAPTPRXDESC_IPPE

◆ ETH_DMAPTPRXDESC_IPHE

◆ ETH_DMAPTPRXDESC_IPPT

◆ ETH_DMAPTPRXDESC_IPPT_UDP

◆ ETH_DMAPTPRXDESC_IPPT_TCP

◆ ETH_DMAPTPRXDESC_IPPT_ICMP

◆ ETH_DMAPTPRXDESC_RTSL

◆ ETH_DMAPTPRXDESC_RTSH