STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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Macros
ETH DMA Tx Descriptor Bit Definition
STM32F4xx_HAL_Driver » ETH » ETH Exported Constants
Collaboration diagram for ETH DMA Tx Descriptor Bit Definition:

Macros

#define ETH_DMATXDESC_OWN   0x80000000U
 Bit definition of TDES0 register: DMA Tx descriptor status register.
 
#define ETH_DMATXDESC_IC   0x40000000U
 
#define ETH_DMATXDESC_LS   0x20000000U
 
#define ETH_DMATXDESC_FS   0x10000000U
 
#define ETH_DMATXDESC_DC   0x08000000U
 
#define ETH_DMATXDESC_DP   0x04000000U
 
#define ETH_DMATXDESC_TTSE   0x02000000U
 
#define ETH_DMATXDESC_CIC   0x00C00000U
 
#define ETH_DMATXDESC_CIC_BYPASS   0x00000000U
 
#define ETH_DMATXDESC_CIC_IPV4HEADER   0x00400000U
 
#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT   0x00800000U
 
#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL   0x00C00000U
 
#define ETH_DMATXDESC_TER   0x00200000U
 
#define ETH_DMATXDESC_TCH   0x00100000U
 
#define ETH_DMATXDESC_TTSS   0x00020000U
 
#define ETH_DMATXDESC_IHE   0x00010000U
 
#define ETH_DMATXDESC_ES   0x00008000U
 
#define ETH_DMATXDESC_JT   0x00004000U
 
#define ETH_DMATXDESC_FF   0x00002000U
 
#define ETH_DMATXDESC_PCE   0x00001000U
 
#define ETH_DMATXDESC_LCA   0x00000800U
 
#define ETH_DMATXDESC_NC   0x00000400U
 
#define ETH_DMATXDESC_LCO   0x00000200U
 
#define ETH_DMATXDESC_EC   0x00000100U
 
#define ETH_DMATXDESC_VF   0x00000080U
 
#define ETH_DMATXDESC_CC   0x00000078U
 
#define ETH_DMATXDESC_ED   0x00000004U
 
#define ETH_DMATXDESC_UF   0x00000002U
 
#define ETH_DMATXDESC_DB   0x00000001U
 
#define ETH_DMATXDESC_TBS2   0x1FFF0000U
 Bit definition of TDES1 register.
 
#define ETH_DMATXDESC_TBS1   0x00001FFFU
 
#define ETH_DMATXDESC_B1AP   0xFFFFFFFFU
 Bit definition of TDES2 register.
 
#define ETH_DMATXDESC_B2AP   0xFFFFFFFFU
 Bit definition of TDES3 register.
 
#define ETH_DMAPTPTXDESC_TTSL   0xFFFFFFFFU /* Transmit Time Stamp Low */
 
#define ETH_DMAPTPTXDESC_TTSH   0xFFFFFFFFU /* Transmit Time Stamp High */
 

Detailed Description

Macro Definition Documentation

◆ ETH_DMATXDESC_OWN

#define ETH_DMATXDESC_OWN   0x80000000U

#include <stm32f4xx_hal_eth.h>

Bit definition of TDES0 register: DMA Tx descriptor status register.

OWN bit: descriptor is owned by DMA engine

Definition at line 695 of file stm32f4xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors(), HAL_ETH_ReleaseTxPacket(), and HAL_ETH_Transmit().

◆ ETH_DMATXDESC_IC

#define ETH_DMATXDESC_IC   0x40000000U

#include <stm32f4xx_hal_eth.h>

Interrupt on Completion

Definition at line 696 of file stm32f4xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

◆ ETH_DMATXDESC_LS

#define ETH_DMATXDESC_LS   0x20000000U

#include <stm32f4xx_hal_eth.h>

Last Segment

Definition at line 697 of file stm32f4xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors(), HAL_ETH_ReleaseTxPacket(), and HAL_ETH_Transmit().

◆ ETH_DMATXDESC_FS

#define ETH_DMATXDESC_FS   0x10000000U

#include <stm32f4xx_hal_eth.h>

First Segment

Definition at line 698 of file stm32f4xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors(), and HAL_ETH_Transmit().

◆ ETH_DMATXDESC_DC

#define ETH_DMATXDESC_DC   0x08000000U

#include <stm32f4xx_hal_eth.h>

Disable CRC

Definition at line 699 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_DP

#define ETH_DMATXDESC_DP   0x04000000U

#include <stm32f4xx_hal_eth.h>

Disable Padding

Definition at line 700 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_TTSE

#define ETH_DMATXDESC_TTSE   0x02000000U

#include <stm32f4xx_hal_eth.h>

Transmit Time Stamp Enable

Definition at line 701 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_CIC

#define ETH_DMATXDESC_CIC   0x00C00000U

#include <stm32f4xx_hal_eth.h>

Checksum Insertion Control: 4 cases

Definition at line 702 of file stm32f4xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

◆ ETH_DMATXDESC_CIC_BYPASS

#define ETH_DMATXDESC_CIC_BYPASS   0x00000000U

#include <stm32f4xx_hal_eth.h>

Do Nothing: Checksum Engine is bypassed

Definition at line 703 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_CIC_IPV4HEADER

#define ETH_DMATXDESC_CIC_IPV4HEADER   0x00400000U

#include <stm32f4xx_hal_eth.h>

IPV4 header Checksum Insertion

Definition at line 704 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT

#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT   0x00800000U

#include <stm32f4xx_hal_eth.h>

TCP/UDP/ICMP Checksum Insertion calculated over segment only

Definition at line 705 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_CIC_TCPUDPICMP_FULL

#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL   0x00C00000U

#include <stm32f4xx_hal_eth.h>

TCP/UDP/ICMP Checksum Insertion fully calculated

Definition at line 706 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_TER

#define ETH_DMATXDESC_TER   0x00200000U

#include <stm32f4xx_hal_eth.h>

Transmit End of Ring

Definition at line 707 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_TCH

#define ETH_DMATXDESC_TCH   0x00100000U

#include <stm32f4xx_hal_eth.h>

Second Address Chained

Definition at line 708 of file stm32f4xx_hal_eth.h.

Referenced by ETH_DMATxDescListInit().

◆ ETH_DMATXDESC_TTSS

#define ETH_DMATXDESC_TTSS   0x00020000U

#include <stm32f4xx_hal_eth.h>

Tx Time Stamp Status

Definition at line 709 of file stm32f4xx_hal_eth.h.

Referenced by HAL_ETH_ReleaseTxPacket().

◆ ETH_DMATXDESC_IHE

#define ETH_DMATXDESC_IHE   0x00010000U

#include <stm32f4xx_hal_eth.h>

IP Header Error

Definition at line 710 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_ES

#define ETH_DMATXDESC_ES   0x00008000U

#include <stm32f4xx_hal_eth.h>

Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT

Definition at line 711 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_JT

#define ETH_DMATXDESC_JT   0x00004000U

#include <stm32f4xx_hal_eth.h>

Jabber Timeout

Definition at line 712 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_FF

#define ETH_DMATXDESC_FF   0x00002000U

#include <stm32f4xx_hal_eth.h>

Frame Flushed: DMA/MTL flushed the frame due to SW flush

Definition at line 713 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_PCE

#define ETH_DMATXDESC_PCE   0x00001000U

#include <stm32f4xx_hal_eth.h>

Payload Checksum Error

Definition at line 714 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_LCA

#define ETH_DMATXDESC_LCA   0x00000800U

#include <stm32f4xx_hal_eth.h>

Loss of Carrier: carrier lost during transmission

Definition at line 715 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_NC

#define ETH_DMATXDESC_NC   0x00000400U

#include <stm32f4xx_hal_eth.h>

No Carrier: no carrier signal from the transceiver

Definition at line 716 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_LCO

#define ETH_DMATXDESC_LCO   0x00000200U

#include <stm32f4xx_hal_eth.h>

Late Collision: transmission aborted due to collision

Definition at line 717 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_EC

#define ETH_DMATXDESC_EC   0x00000100U

#include <stm32f4xx_hal_eth.h>

Excessive Collision: transmission aborted after 16 collisions

Definition at line 718 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_VF

#define ETH_DMATXDESC_VF   0x00000080U

#include <stm32f4xx_hal_eth.h>

VLAN Frame

Definition at line 719 of file stm32f4xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

◆ ETH_DMATXDESC_CC

#define ETH_DMATXDESC_CC   0x00000078U

#include <stm32f4xx_hal_eth.h>

Collision Count

Definition at line 720 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_ED

#define ETH_DMATXDESC_ED   0x00000004U

#include <stm32f4xx_hal_eth.h>

Excessive Deferral

Definition at line 721 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_UF

#define ETH_DMATXDESC_UF   0x00000002U

#include <stm32f4xx_hal_eth.h>

Underflow Error: late data arrival from the memory

Definition at line 722 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_DB

#define ETH_DMATXDESC_DB   0x00000001U

#include <stm32f4xx_hal_eth.h>

Deferred Bit

Definition at line 723 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_TBS2

#define ETH_DMATXDESC_TBS2   0x1FFF0000U

#include <stm32f4xx_hal_eth.h>

Bit definition of TDES1 register.

Transmit Buffer2 Size

Definition at line 728 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_TBS1

#define ETH_DMATXDESC_TBS1   0x00001FFFU

#include <stm32f4xx_hal_eth.h>

Transmit Buffer1 Size

Definition at line 729 of file stm32f4xx_hal_eth.h.

Referenced by ETH_Prepare_Tx_Descriptors().

◆ ETH_DMATXDESC_B1AP

#define ETH_DMATXDESC_B1AP   0xFFFFFFFFU

#include <stm32f4xx_hal_eth.h>

Bit definition of TDES2 register.

Buffer1 Address Pointer

Definition at line 734 of file stm32f4xx_hal_eth.h.

◆ ETH_DMATXDESC_B2AP

#define ETH_DMATXDESC_B2AP   0xFFFFFFFFU

#include <stm32f4xx_hal_eth.h>

Bit definition of TDES3 register.

Buffer2 Address Pointer

Definition at line 739 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPTXDESC_TTSL

#define ETH_DMAPTPTXDESC_TTSL   0xFFFFFFFFU /* Transmit Time Stamp Low */

#include <stm32f4xx_hal_eth.h>

Definition at line 748 of file stm32f4xx_hal_eth.h.

◆ ETH_DMAPTPTXDESC_TTSH

#define ETH_DMAPTPTXDESC_TTSH   0xFFFFFFFFU /* Transmit Time Stamp High */

#include <stm32f4xx_hal_eth.h>

Definition at line 751 of file stm32f4xx_hal_eth.h.