20#ifndef STM32F4xx_HAL_CEC_H
21#define STM32F4xx_HAL_CEC_H
166#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
167typedef struct __CEC_HandleTypeDef
194#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
195 void (* TxCpltCallback)(
struct __CEC_HandleTypeDef
197 void (* RxCpltCallback)(
struct __CEC_HandleTypeDef *hcec,
198 uint32_t RxFrameSize);
199 void (* ErrorCallback)(
struct __CEC_HandleTypeDef *hcec);
201 void (* MspInitCallback)(
struct __CEC_HandleTypeDef *hcec);
202 void (* MspDeInitCallback)(
struct __CEC_HandleTypeDef *hcec);
207#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
213 HAL_CEC_TX_CPLT_CB_ID = 0x00U,
214 HAL_CEC_RX_CPLT_CB_ID = 0x01U,
215 HAL_CEC_ERROR_CB_ID = 0x02U,
216 HAL_CEC_MSPINIT_CB_ID = 0x03U,
217 HAL_CEC_MSPDEINIT_CB_ID = 0x04U
218} HAL_CEC_CallbackIDTypeDef;
225 uint32_t RxFrameSize);
239#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000)
241#define HAL_CEC_STATE_READY ((uint32_t)0x00000020)
243#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024)
245#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022)
247#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021)
249#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023)
251#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050)
258#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U
259#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR
260#define HAL_CEC_ERROR_BRE CEC_ISR_BRE
261#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE
262#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE
263#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE
264#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST
265#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR
266#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR
267#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE
268#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
269#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U)
278#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
279#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
280#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
281#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
282#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
283#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
284#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
285#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
293#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
294#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
302#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
303#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
311#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
312#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
320#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
321#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
329#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
330#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
338#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
339#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
347#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
348#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
356#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
364#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
372#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U)
373#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U)
374#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U)
375#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U)
376#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U)
377#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U)
378#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U)
379#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U)
380#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U)
381#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U)
382#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U)
383#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U)
384#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U)
385#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U)
386#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U)
387#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U)
395#define CEC_IT_TXACKE CEC_IER_TXACKEIE
396#define CEC_IT_TXERR CEC_IER_TXERRIE
397#define CEC_IT_TXUDR CEC_IER_TXUDRIE
398#define CEC_IT_TXEND CEC_IER_TXENDIE
399#define CEC_IT_TXBR CEC_IER_TXBRIE
400#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
401#define CEC_IT_RXACKE CEC_IER_RXACKEIE
402#define CEC_IT_LBPE CEC_IER_LBPEIE
403#define CEC_IT_SBPE CEC_IER_SBPEIE
404#define CEC_IT_BRE CEC_IER_BREIE
405#define CEC_IT_RXOVR CEC_IER_RXOVRIE
406#define CEC_IT_RXEND CEC_IER_RXENDIE
407#define CEC_IT_RXBR CEC_IER_RXBRIE
415#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
416#define CEC_FLAG_TXERR CEC_ISR_TXERR
417#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
418#define CEC_FLAG_TXEND CEC_ISR_TXEND
419#define CEC_FLAG_TXBR CEC_ISR_TXBR
420#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
421#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
422#define CEC_FLAG_LBPE CEC_ISR_LBPE
423#define CEC_FLAG_SBPE CEC_ISR_SBPE
424#define CEC_FLAG_BRE CEC_ISR_BRE
425#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
426#define CEC_FLAG_RXEND CEC_ISR_RXEND
427#define CEC_FLAG_RXBR CEC_ISR_RXBR
435#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
436 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
444#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
452#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
470#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
471#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
472 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
473 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
474 (__HANDLE__)->MspInitCallback = NULL; \
475 (__HANDLE__)->MspDeInitCallback = NULL; \
478#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
479 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
480 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
501#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
522#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
543#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
564#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
585#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
591#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
597#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
603#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
610#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
616#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
622#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
628#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
636#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \
637 (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
658#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
660 pCEC_CallbackTypeDef pCallback);
675 const uint8_t *pData, uint32_t Size);
732#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
734#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
735 ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
737#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
738 ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
740#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
741 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
743#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
744 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
746#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \
747 (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
748 ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
750#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
751 ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
753#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
754 ((__MODE__) == CEC_FULL_LISTENING_MODE))
763#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
770#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
777#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
CEC MSP DeInit.
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
CEC MSP Init.
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
DeInitializes the CEC peripheral.
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
Initializes the CEC mode according to the specified parameters in the CEC_InitTypeDef and creates the...
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
Initializes the Own Address of the CEC device.
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
Tx Transfer completed callback.
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
This function handles CEC interrupt requests.
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
CEC error callbacks.
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec)
Get size of the received frame.
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
Rx Transfer completed callback.
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, const uint8_t *pData, uint32_t Size)
Send data in interrupt mode.
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
Change Rx Buffer.
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec)
Return the CEC error code.
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec)
return the CEC state
uint32_t HAL_CEC_StateTypeDef
HAL CEC State definition.
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition
HAL_LockTypeDef
HAL Lock structures definition
CEC handle Structure definition.
HAL_CEC_StateTypeDef gState
HAL_CEC_StateTypeDef RxState
const uint8_t * pTxBuffPtr
CEC Init Structure definition.
uint32_t BroadcastMsgNoErrorBitGen
uint32_t SignalFreeTimeOption