stm32f4xx_hal_sdram.c

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/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
 
#if defined(FMC_Bank5_6)
 
#ifdef HAL_SDRAM_MODULE_ENABLED
 
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma);
static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
static void SDRAM_DMAError(DMA_HandleTypeDef *hdma);
/* Exported functions --------------------------------------------------------*/
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
{
  /* Check the SDRAM handle parameter */
  if (hsdram == NULL)
  {
    return HAL_ERROR;
  }
 
  if (hsdram->State == HAL_SDRAM_STATE_RESET)
  {
    /* Allocate lock resource and initialize it */
    hsdram->Lock = HAL_UNLOCKED;
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
    if (hsdram->MspInitCallback == NULL)
    {
      hsdram->MspInitCallback = HAL_SDRAM_MspInit;
    }
    hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
    hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
    hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
 
    /* Init the low level hardware */
    hsdram->MspInitCallback(hsdram);
#else
    /* Initialize the low level hardware (MSP) */
    HAL_SDRAM_MspInit(hsdram);
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
  }
 
  /* Initialize the SDRAM controller state */
  hsdram->State = HAL_SDRAM_STATE_BUSY;
 
  /* Initialize SDRAM control Interface */
  (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
 
  /* Initialize SDRAM timing Interface */
  (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
  /* Update the SDRAM controller state */
  hsdram->State = HAL_SDRAM_STATE_READY;
 
  return HAL_OK;
}
 
HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
{
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
  if (hsdram->MspDeInitCallback == NULL)
  {
    hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
  }
 
  /* DeInit the low level hardware */
  hsdram->MspDeInitCallback(hsdram);
#else
  /* Initialize the low level hardware (MSP) */
  HAL_SDRAM_MspDeInit(hsdram);
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
 
  /* Configure the SDRAM registers with their reset values */
  (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
 
  /* Reset the SDRAM controller state */
  hsdram->State = HAL_SDRAM_STATE_RESET;
 
  /* Release Lock */
  __HAL_UNLOCK(hsdram);
 
  return HAL_OK;
}
 
__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
{
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hsdram);
 
  /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_SDRAM_MspInit could be implemented in the user file
   */
}
 
__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
{
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hsdram);
 
  /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_SDRAM_MspDeInit could be implemented in the user file
   */
}
 
void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
{
  /* Check SDRAM interrupt Rising edge flag */
  if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
  {
    /* SDRAM refresh error interrupt callback */
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
    hsdram->RefreshErrorCallback(hsdram);
#else
    HAL_SDRAM_RefreshErrorCallback(hsdram);
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
 
    /* Clear SDRAM refresh error interrupt pending bit */
    __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
  }
}
 
__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
{
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hsdram);
 
  /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
   */
}
 
__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
{
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hdma);
 
  /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
   */
}
 
__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
{
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hdma);
 
  /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
   */
}
 
HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
                                    uint32_t BufferSize)
{
  uint32_t size;
  __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
  uint8_t *pdestbuff = pDstBuffer;
  HAL_SDRAM_StateTypeDef state = hsdram->State;
 
  /* Check the SDRAM controller state */
  if (state == HAL_SDRAM_STATE_BUSY)
  {
    return HAL_BUSY;
  }
  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  {
    /* Process Locked */
    __HAL_LOCK(hsdram);
 
    /* Update the SDRAM controller state */
    hsdram->State = HAL_SDRAM_STATE_BUSY;
 
    /* Read data from source */
    for (size = BufferSize; size != 0U; size--)
    {
      *pdestbuff = *(__IO uint8_t *)pSdramAddress;
      pdestbuff++;
      pSdramAddress++;
    }
 
    /* Update the SDRAM controller state */
    hsdram->State = state;
 
    /* Process Unlocked */
    __HAL_UNLOCK(hsdram);
  }
  else
  {
    return  HAL_ERROR;
  }
 
  return HAL_OK;
}
 
HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
                                     uint32_t BufferSize)
{
  uint32_t size;
  __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
  uint8_t *psrcbuff = pSrcBuffer;
 
  /* Check the SDRAM controller state */
  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  {
    return HAL_BUSY;
  }
  else if (hsdram->State == HAL_SDRAM_STATE_READY)
  {
    /* Process Locked */
    __HAL_LOCK(hsdram);
 
    /* Update the SDRAM controller state */
    hsdram->State = HAL_SDRAM_STATE_BUSY;
 
    /* Write data to memory */
    for (size = BufferSize; size != 0U; size--)
    {
      *(__IO uint8_t *)pSdramAddress = *psrcbuff;
      psrcbuff++;
      pSdramAddress++;
    }
 
    /* Update the SDRAM controller state */
    hsdram->State = HAL_SDRAM_STATE_READY;
 
    /* Process Unlocked */
    __HAL_UNLOCK(hsdram);
  }
  else
  {
    return  HAL_ERROR;
  }
 
  return HAL_OK;
}
 
HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
                                     uint32_t BufferSize)
{
  uint32_t size;
  __IO uint32_t *pSdramAddress = pAddress;
  uint16_t *pdestbuff = pDstBuffer;
  HAL_SDRAM_StateTypeDef state = hsdram->State;
 
  /* Check the SDRAM controller state */
  if (state == HAL_SDRAM_STATE_BUSY)
  {
    return HAL_BUSY;
  }
  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  {
    /* Process Locked */
    __HAL_LOCK(hsdram);
 
    /* Update the SDRAM controller state */
    hsdram->State = HAL_SDRAM_STATE_BUSY;
 
    /* Read data from memory */
    for (size = BufferSize; size >= 2U ; size -= 2U)
    {
      *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
      pdestbuff++;
      *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
      pdestbuff++;
      pSdramAddress++;
    }
 
    /* Read last 16-bits if size is not 32-bits multiple */
    if ((BufferSize % 2U) != 0U)
    {
      *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
    }
 
    /* Update the SDRAM controller state */
    hsdram->State = state;
 
    /* Process Unlocked */
    __HAL_UNLOCK(hsdram);
  }
  else
  {
    return  HAL_ERROR;
  }
 
  return HAL_OK;
}
 
HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
                                      uint32_t BufferSize)
{
  uint32_t size;
  __IO uint32_t *psdramaddress = pAddress;
  uint16_t *psrcbuff = pSrcBuffer;
 
  /* Check the SDRAM controller state */
  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  {
    return HAL_BUSY;
  }
  else if (hsdram->State == HAL_SDRAM_STATE_READY)
  {
    /* Process Locked */
    __HAL_LOCK(hsdram);
 
    /* Update the SDRAM controller state */
    hsdram->State = HAL_SDRAM_STATE_BUSY;
 
    /* Write data to memory */
    for (size = BufferSize; size >= 2U ; size -= 2U)
    {
      *psdramaddress = (uint32_t)(*psrcbuff);
      psrcbuff++;
      *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
      psrcbuff++;
      psdramaddress++;
    }
 
    /* Write last 16-bits if size is not 32-bits multiple */
    if ((BufferSize % 2U) != 0U)
    {
      *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
    }
 
    /* Update the SDRAM controller state */
    hsdram->State = HAL_SDRAM_STATE_READY;
 
    /* Process Unlocked */
    __HAL_UNLOCK(hsdram);
  }
  else
  {
    return  HAL_ERROR;
  }
 
  return HAL_OK;
}
 
HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
                                     uint32_t BufferSize)
{
  uint32_t size;
  __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
  uint32_t *pdestbuff = pDstBuffer;
  HAL_SDRAM_StateTypeDef state = hsdram->State;
 
  /* Check the SDRAM controller state */
  if (state == HAL_SDRAM_STATE_BUSY)
  {
    return HAL_BUSY;
  }
  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  {
    /* Process Locked */
    __HAL_LOCK(hsdram);
 
    /* Update the SDRAM controller state */
    hsdram->State = HAL_SDRAM_STATE_BUSY;
 
    /* Read data from source */
    for (size = BufferSize; size != 0U; size--)
    {
      *pdestbuff = *(__IO uint32_t *)pSdramAddress;
      pdestbuff++;
      pSdramAddress++;
    }
 
    /* Update the SDRAM controller state */
    hsdram->State = state;
 
    /* Process Unlocked */
    __HAL_UNLOCK(hsdram);
  }
  else
  {
    return  HAL_ERROR;
  }
 
  return HAL_OK;
}
 
HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
                                      uint32_t BufferSize)
{
  uint32_t size;
  __IO uint32_t *pSdramAddress = pAddress;
  uint32_t *psrcbuff = pSrcBuffer;
 
  /* Check the SDRAM controller state */
  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  {
    return HAL_BUSY;
  }
  else if (hsdram->State == HAL_SDRAM_STATE_READY)
  {
    /* Process Locked */
    __HAL_LOCK(hsdram);
 
    /* Update the SDRAM controller state */
    hsdram->State = HAL_SDRAM_STATE_BUSY;
 
    /* Write data to memory */
    for (size = BufferSize; size != 0U; size--)
    {
      *pSdramAddress = *psrcbuff;
      psrcbuff++;
      pSdramAddress++;
    }
 
    /* Update the SDRAM controller state */
    hsdram->State = HAL_SDRAM_STATE_READY;
 
    /* Process Unlocked */
    __HAL_UNLOCK(hsdram);
  }
  else
  {
    return  HAL_ERROR;
  }
 
  return HAL_OK;
}
 
HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
                                     uint32_t BufferSize)
{
  HAL_StatusTypeDef status;
  HAL_SDRAM_StateTypeDef state = hsdram->State;
 
  /* Check the SDRAM controller state */
  if (state == HAL_SDRAM_STATE_BUSY)
  {
    status = HAL_BUSY;
  }
  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  {
    /* Process Locked */
    __HAL_LOCK(hsdram);
 
    /* Update the SDRAM controller state */
    hsdram->State = HAL_SDRAM_STATE_BUSY;
 
    /* Configure DMA user callbacks */
    if (state == HAL_SDRAM_STATE_READY)
    {
      hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
    }
    else
    {
      hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt;
    }
    hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
 
    /* Enable the DMA Stream */
    status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
 
    /* Process Unlocked */
    __HAL_UNLOCK(hsdram);
  }
  else
  {
    status = HAL_ERROR;
  }
 
  return status;
}
 
HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
                                      uint32_t BufferSize)
{
  HAL_StatusTypeDef status;
 
  /* Check the SDRAM controller state */
  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  {
    status = HAL_BUSY;
  }
  else if (hsdram->State == HAL_SDRAM_STATE_READY)
  {
    /* Process Locked */
    __HAL_LOCK(hsdram);
 
    /* Update the SDRAM controller state */
    hsdram->State = HAL_SDRAM_STATE_BUSY;
 
    /* Configure DMA user callbacks */
    hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
    hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
 
    /* Enable the DMA Stream */
    status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
 
    /* Process Unlocked */
    __HAL_UNLOCK(hsdram);
  }
  else
  {
    status = HAL_ERROR;
  }
 
  return status;
}
 
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
                                             pSDRAM_CallbackTypeDef pCallback)
{
  HAL_StatusTypeDef status = HAL_OK;
  HAL_SDRAM_StateTypeDef state;
 
  if (pCallback == NULL)
  {
    return HAL_ERROR;
  }
 
  state = hsdram->State;
  if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  {
    switch (CallbackId)
    {
      case HAL_SDRAM_MSP_INIT_CB_ID :
        hsdram->MspInitCallback = pCallback;
        break;
      case HAL_SDRAM_MSP_DEINIT_CB_ID :
        hsdram->MspDeInitCallback = pCallback;
        break;
      case HAL_SDRAM_REFRESH_ERR_CB_ID :
        hsdram->RefreshErrorCallback = pCallback;
        break;
      default :
        /* update return status */
        status =  HAL_ERROR;
        break;
    }
  }
  else if (hsdram->State == HAL_SDRAM_STATE_RESET)
  {
    switch (CallbackId)
    {
      case HAL_SDRAM_MSP_INIT_CB_ID :
        hsdram->MspInitCallback = pCallback;
        break;
      case HAL_SDRAM_MSP_DEINIT_CB_ID :
        hsdram->MspDeInitCallback = pCallback;
        break;
      default :
        /* update return status */
        status =  HAL_ERROR;
        break;
    }
  }
  else
  {
    /* update return status */
    status =  HAL_ERROR;
  }
 
  return status;
}
 
HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
{
  HAL_StatusTypeDef status = HAL_OK;
  HAL_SDRAM_StateTypeDef state;
 
  state = hsdram->State;
  if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  {
    switch (CallbackId)
    {
      case HAL_SDRAM_MSP_INIT_CB_ID :
        hsdram->MspInitCallback = HAL_SDRAM_MspInit;
        break;
      case HAL_SDRAM_MSP_DEINIT_CB_ID :
        hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
        break;
      case HAL_SDRAM_REFRESH_ERR_CB_ID :
        hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
        break;
      case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
        hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
        break;
      case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
        hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
        break;
      default :
        /* update return status */
        status =  HAL_ERROR;
        break;
    }
  }
  else if (hsdram->State == HAL_SDRAM_STATE_RESET)
  {
    switch (CallbackId)
    {
      case HAL_SDRAM_MSP_INIT_CB_ID :
        hsdram->MspInitCallback = HAL_SDRAM_MspInit;
        break;
      case HAL_SDRAM_MSP_DEINIT_CB_ID :
        hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
        break;
      default :
        /* update return status */
        status =  HAL_ERROR;
        break;
    }
  }
  else
  {
    /* update return status */
    status =  HAL_ERROR;
  }
 
  return status;
}
 
HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
                                                pSDRAM_DmaCallbackTypeDef pCallback)
{
  HAL_StatusTypeDef status = HAL_OK;
  HAL_SDRAM_StateTypeDef state;
 
  if (pCallback == NULL)
  {
    return HAL_ERROR;
  }
 
  /* Process locked */
  __HAL_LOCK(hsdram);
 
  state = hsdram->State;
  if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  {
    switch (CallbackId)
    {
      case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
        hsdram->DmaXferCpltCallback = pCallback;
        break;
      case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
        hsdram->DmaXferErrorCallback = pCallback;
        break;
      default :
        /* update return status */
        status =  HAL_ERROR;
        break;
    }
  }
  else
  {
    /* update return status */
    status =  HAL_ERROR;
  }
 
  /* Release Lock */
  __HAL_UNLOCK(hsdram);
  return status;
}
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
 
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
{
  /* Check the SDRAM controller state */
  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  {
    return HAL_BUSY;
  }
  else if (hsdram->State == HAL_SDRAM_STATE_READY)
  {
    /* Update the SDRAM state */
    hsdram->State = HAL_SDRAM_STATE_BUSY;
 
    /* Enable write protection */
    (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
 
    /* Update the SDRAM state */
    hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
  }
  else
  {
    return HAL_ERROR;
  }
 
  return HAL_OK;
}
 
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
{
  HAL_SDRAM_StateTypeDef state = hsdram->State;
 
  /* Check the SDRAM controller state */
  if (state == HAL_SDRAM_STATE_BUSY)
  {
    return HAL_BUSY;
  }
  else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
  {
    /* Update the SDRAM state */
    hsdram->State = HAL_SDRAM_STATE_BUSY;
 
    /* Disable write protection */
    (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
 
    /* Update the SDRAM state */
    hsdram->State = HAL_SDRAM_STATE_READY;
  }
  else
  {
    return HAL_ERROR;
  }
 
  return HAL_OK;
}
 
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
                                        uint32_t Timeout)
{
  HAL_SDRAM_StateTypeDef state = hsdram->State;
 
  /* Check the SDRAM controller state */
  if (state == HAL_SDRAM_STATE_BUSY)
  {
    return HAL_BUSY;
  }
  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
  {
    /* Update the SDRAM state */
    hsdram->State = HAL_SDRAM_STATE_BUSY;
 
    /* Send SDRAM command */
    (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
 
    /* Update the SDRAM controller state state */
    if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
    {
      hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
    }
    else
    {
      hsdram->State = HAL_SDRAM_STATE_READY;
    }
  }
  else
  {
    return HAL_ERROR;
  }
 
  return HAL_OK;
}
 
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
{
  /* Check the SDRAM controller state */
  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  {
    return HAL_BUSY;
  }
  else if (hsdram->State == HAL_SDRAM_STATE_READY)
  {
    /* Update the SDRAM state */
    hsdram->State = HAL_SDRAM_STATE_BUSY;
 
    /* Program the refresh rate */
    (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
 
    /* Update the SDRAM state */
    hsdram->State = HAL_SDRAM_STATE_READY;
  }
  else
  {
    return HAL_ERROR;
  }
 
  return HAL_OK;
}
 
HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
{
  /* Check the SDRAM controller state */
  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  {
    return HAL_BUSY;
  }
  else if (hsdram->State == HAL_SDRAM_STATE_READY)
  {
    /* Update the SDRAM state */
    hsdram->State = HAL_SDRAM_STATE_BUSY;
 
    /* Set the Auto-Refresh number */
    (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
 
    /* Update the SDRAM state */
    hsdram->State = HAL_SDRAM_STATE_READY;
  }
  else
  {
    return HAL_ERROR;
  }
 
  return HAL_OK;
}
 
uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
{
  /* Return the SDRAM memory current mode */
  return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
}
 
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
{
  return hsdram->State;
}
 
static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
{
  SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
 
  /* Disable the DMA channel */
  __HAL_DMA_DISABLE(hdma);
 
  /* Update the SDRAM controller state */
  hsdram->State = HAL_SDRAM_STATE_READY;
 
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
  hsdram->DmaXferCpltCallback(hdma);
#else
  HAL_SDRAM_DMA_XferCpltCallback(hdma);
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
}
 
static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
{
  SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
 
  /* Disable the DMA channel */
  __HAL_DMA_DISABLE(hdma);
 
  /* Update the SDRAM controller state */
  hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
 
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
  hsdram->DmaXferCpltCallback(hdma);
#else
  HAL_SDRAM_DMA_XferCpltCallback(hdma);
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
}
 
static void SDRAM_DMAError(DMA_HandleTypeDef *hdma)
{
  SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
 
  /* Disable the DMA channel */
  __HAL_DMA_DISABLE(hdma);
 
  /* Update the SDRAM controller state */
  hsdram->State = HAL_SDRAM_STATE_ERROR;
 
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
  hsdram->DmaXferErrorCallback(hdma);
#else
  HAL_SDRAM_DMA_XferErrorCallback(hdma);
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
}
 
#endif /* HAL_SDRAM_MODULE_ENABLED */
 
#endif /* FMC_Bank5_6 */