STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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RCC_PLLSAIInitTypeDef Struct Reference

PLLSAI Clock structure definition. More...

#include <stm32f4xx_hal_rcc_ex.h>

Collaboration diagram for RCC_PLLSAIInitTypeDef:

Data Fields

uint32_t PLLSAIM
 
uint32_t PLLSAIN
 
uint32_t PLLSAIP
 
uint32_t PLLSAIQ
 

Detailed Description

PLLSAI Clock structure definition.

Definition at line 102 of file stm32f4xx_hal_rcc_ex.h.

Field Documentation

◆ PLLSAIM

uint32_t RCC_PLLSAIInitTypeDef::PLLSAIM

Specifies division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 2 and Max_Data = 63

Definition at line 104 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

◆ PLLSAIN

uint32_t RCC_PLLSAIInitTypeDef::PLLSAIN

Specifies the multiplication factor for PLLI2S VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432

Definition at line 107 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

◆ PLLSAIP

uint32_t RCC_PLLSAIInitTypeDef::PLLSAIP

Specifies division factor for OTG FS, SDIO and RNG clocks. This parameter must be a value of RCC PLLSAIP Clock Divider

Definition at line 110 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

◆ PLLSAIQ

uint32_t RCC_PLLSAIInitTypeDef::PLLSAIQ

Specifies the division factor for SAI clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15. This parameter will be used only when PLLSAI is selected as Clock Source SAI

Definition at line 113 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().


The documentation for this struct was generated from the following file: