STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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AHB3 Peripheral Clock Enable Disable

Enables or disables the AHB3 peripheral clock. More...

Collaboration diagram for AHB3 Peripheral Clock Enable Disable:

Macros

#define __HAL_RCC_FMC_CLK_ENABLE()
 
#define __HAL_RCC_QSPI_CLK_ENABLE()
 
#define __HAL_RCC_FMC_CLK_DISABLE()
 
#define __HAL_RCC_QSPI_CLK_DISABLE()
 

Detailed Description

Enables or disables the AHB3 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

◆ __HAL_RCC_FMC_CLK_ENABLE

#define __HAL_RCC_FMC_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 4126 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_QSPI_CLK_ENABLE

#define __HAL_RCC_QSPI_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 4133 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_FMC_CLK_DISABLE

#define __HAL_RCC_FMC_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
(RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))

Definition at line 4141 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_QSPI_CLK_DISABLE

#define __HAL_RCC_QSPI_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
(RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))

Definition at line 4142 of file stm32f4xx_hal_rcc_ex.h.