RCCEx Exported Macros

Topics
	AHB1 Peripheral Clock Enable Disable
	Enables or disables the AHB1 peripheral clock.
	AHB1 Peripheral Clock Enable Disable Status
	Get the enable or disable status of the AHB1 peripheral clock.
	AHB2 Peripheral Clock Enable Disable
	Enable or disable the AHB2 peripheral clock.
	AHB2 Peripheral Clock Enable Disable Status
	Get the enable or disable status of the AHB2 peripheral clock.
	AHB3 Peripheral Clock Enable Disable
	Enables or disables the AHB3 peripheral clock.
	AHB3 Peripheral Clock Enable Disable Status
	Get the enable or disable status of the AHB3 peripheral clock.
	APB1 Peripheral Clock Enable Disable
	Enable or disable the Low Speed APB (APB1) peripheral clock.
	APB1 Peripheral Clock Enable Disable Status
	Get the enable or disable status of the APB1 peripheral clock.
	APB2 Peripheral Clock Enable Disable
	Enable or disable the High Speed APB (APB2) peripheral clock.
	APB2 Peripheral Clock Enable Disable Status
	Get the enable or disable status of the APB2 peripheral clock.
	AHB1 Force Release Reset
	Force or release AHB1 peripheral reset.
	AHB2 Force Release Reset
	Force or release AHB2 peripheral reset.
	AHB3 Force Release Reset
	Force or release AHB3 peripheral reset.
	APB1 Force Release Reset
	Force or release APB1 peripheral reset.
	APB2 Force Release Reset
	Force or release APB2 peripheral reset.
	AHB1 Peripheral Low Power Enable Disable
	Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
	AHB2 Peripheral Low Power Enable Disable
	Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
	AHB3 Peripheral Low Power Enable Disable
	Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
	APB1 Peripheral Low Power Enable Disable
	Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
	APB2 Peripheral Low Power Enable Disable
	Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

Macros
#define	__HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__, __PLLR__)
	Macro to configure the main PLL clock source, multiplication and division factors.
#define	__HAL_RCC_PLLI2S_ENABLE()
	Macros to enable or disable the PLLI2S.
#define	__HAL_RCC_PLLI2S_DISABLE()
#define	__HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)
	Macro to configure the PLLI2S clock multiplication and division factors .
#define	__HAL_RCC_PLLSAI_ENABLE()
	Macros to Enable or Disable the PLLISAI.
#define	__HAL_RCC_PLLSAI_DISABLE()
#define	__HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)
	Macro to configure the PLLSAI clock multiplication and division factors.
#define	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__)
	Macro to configure the SAI clock Divider coming from PLLI2S.
#define	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__)
	Macro to configure the SAI clock Divider coming from PLLSAI.
#define	__HAL_RCC_SAI1_CONFIG(__SOURCE__)
	Macro to configure SAI1 clock source selection.
#define	__HAL_RCC_GET_SAI1_SOURCE()
	Macro to Get SAI1 clock source selection.
#define	__HAL_RCC_SAI2_CONFIG(__SOURCE__)
	Macro to configure SAI2 clock source selection.
#define	__HAL_RCC_GET_SAI2_SOURCE()
	Macro to Get SAI2 clock source selection.
#define	__HAL_RCC_I2S_APB1_CONFIG(__SOURCE__)
	Macro to configure I2S APB1 clock source selection.
#define	__HAL_RCC_GET_I2S_APB1_SOURCE()
	Macro to Get I2S APB1 clock source selection.
#define	__HAL_RCC_I2S_APB2_CONFIG(__SOURCE__)
	Macro to configure I2S APB2 clock source selection.
#define	__HAL_RCC_GET_I2S_APB2_SOURCE()
	Macro to Get I2S APB2 clock source selection.
#define	__HAL_RCC_CEC_CONFIG(__SOURCE__)
	Macro to configure the CEC clock.
#define	__HAL_RCC_GET_CEC_SOURCE()
	Macro to Get the CEC clock.
#define	__HAL_RCC_FMPI2C1_CONFIG(__SOURCE__)
	Macro to configure the FMPI2C1 clock.
#define	__HAL_RCC_GET_FMPI2C1_SOURCE()
	Macro to Get the FMPI2C1 clock.
#define	__HAL_RCC_CLK48_CONFIG(__SOURCE__)
	Macro to configure the CLK48 clock.
#define	__HAL_RCC_GET_CLK48_SOURCE()
	Macro to Get the CLK48 clock.
#define	__HAL_RCC_SDIO_CONFIG(__SOURCE__)
	Macro to configure the SDIO clock.
#define	__HAL_RCC_GET_SDIO_SOURCE()
	Macro to Get the SDIO clock.
#define	__HAL_RCC_SPDIFRX_CONFIG(__SOURCE__)
	Macro to configure the SPDIFRX clock.
#define	__HAL_RCC_GET_SPDIFRX_SOURCE()
	Macro to Get the SPDIFRX clock.
#define	__HAL_RCC_TIMCLKPRESCALER(__PRESC__)
	Macro to configure the Timers clocks prescalers.
#define	__HAL_RCC_PLLSAI_ENABLE_IT()
	Enable PLLSAI_RDY interrupt.
#define	__HAL_RCC_PLLSAI_DISABLE_IT()
	Disable PLLSAI_RDY interrupt.
#define	__HAL_RCC_PLLSAI_CLEAR_IT()
	Clear the PLLSAI RDY interrupt pending bits.
#define	__HAL_RCC_PLLSAI_GET_IT()
	Check the PLLSAI RDY interrupt has occurred or not.
#define	__HAL_RCC_PLLSAI_GET_FLAG()
	Check PLLSAI RDY flag is set or not.

Detailed Description

Macro Definition Documentation

__HAL_RCC_PLL_CONFIG

#define __HAL_RCC_PLL_CONFIG	(		__RCC_PLLSource__,
			__PLLM__,
			__PLLN__,
			__PLLP__,
			__PLLQ__,
			__PLLR__ )

#include <stm32f4xx_hal_rcc_ex.h>

Value:

  (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__)                   | \
                   ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                      | \
                   ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos)          | \
                   ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)                      | \
                   ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))

Macro to configure the main PLL clock source, multiplication and division factors.

Note

This function must be used only when the main PLL is disabled.

Parameters

__RCC_PLLSource__

specifies the PLL entry clock source. This parameter can be one of the following values: RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

Note

This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.

Parameters

__PLLM__

specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

Note

You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.

Parameters

__PLLN__

specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432.

Note

You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz.

Parameters

__PLLP__	specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.
__PLLQ__	specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15.

Note

If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.

Parameters

__PLLR__

PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. This parameter must be a number between Min_Data = 2 and Max_Data = 7.

Note

This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/ STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.

Definition at line 5834 of file stm32f4xx_hal_rcc_ex.h.

__HAL_RCC_PLLI2S_ENABLE

#define __HAL_RCC_PLLI2S_ENABLE

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)

Macros to enable or disable the PLLI2S.

Note

The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 5888 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_PLLI2S_DISABLE

#define __HAL_RCC_PLLI2S_DISABLE

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)

Definition at line 5889 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_PLLI2S_CONFIG

#define __HAL_RCC_PLLI2S_CONFIG	(		__PLLI2SM__,
			__PLLI2SN__,
			__PLLI2SP__,
			__PLLI2SQ__,
			__PLLI2SR__ )

#include <stm32f4xx_hal_rcc_ex.h>

Value:

  (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                   |\
                      ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)             |\
                      ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\
                      ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos)             |\
                      ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))

Macro to configure the PLLI2S clock multiplication and division factors .

Note

This macro must be used only when the PLLI2S is disabled.

PLLI2S clock source is common with the main PLL (configured in HAL_RCC_ClockConfig() API).

Parameters

__PLLI2SM__

specifies the division factor for PLLI2S VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

Note

You have to set the PLLI2SM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 1 MHz to limit PLLI2S jitter.

Parameters

__PLLI2SN__

specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432.

Note

You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.

Parameters

__PLLI2SP__

specifies division factor for SPDIFRX Clock. This parameter must be a number in the range {2, 4, 6, or 8}.

Note

the PLLI2SP parameter is only available with STM32F446xx Devices

Parameters

__PLLI2SR__

specifies the division factor for I2S clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.

Note

You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.

Parameters

__PLLI2SQ__

specifies the division factor for SAI clock This parameter must be a number between Min_Data = 2 and Max_Data = 15.

Definition at line 5922 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_PLLSAI_ENABLE

#define __HAL_RCC_PLLSAI_ENABLE

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)

Macros to Enable or Disable the PLLISAI.

Note

The PLLSAI is only available with STM32F429x/439x Devices.

The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 6035 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_PLLSAI_DISABLE

#define __HAL_RCC_PLLSAI_DISABLE

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)

Definition at line 6036 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_PLLSAI_CONFIG

#define __HAL_RCC_PLLSAI_CONFIG	(		__PLLSAIM__,
			__PLLSAIN__,
			__PLLSAIP__,
			__PLLSAIQ__,
			__PLLSAIR__ )

#include <stm32f4xx_hal_rcc_ex.h>

Value:

  (RCC->PLLSAICFGR = ((__PLLSAIM__)                                   | \
                      ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)             | \
                      ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \
                      ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)))

Macro to configure the PLLSAI clock multiplication and division factors.

Parameters

__PLLSAIM__

specifies the division factor for PLLSAI VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

Note

You have to set the PLLSAIM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 1 MHz to limit PLLI2S jitter.

The PLLSAIM parameter is only used with STM32F446xx Devices

Parameters

__PLLSAIN__

specifies the multiplication factor for PLLSAI VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432.

Note

You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.

Parameters

__PLLSAIP__

specifies division factor for OTG FS, SDIO and RNG clocks. This parameter must be a number in the range {2, 4, 6, or 8}.

Note

the PLLSAIP parameter is only available with STM32F446xx Devices

Parameters

__PLLSAIQ__	specifies the division factor for SAI clock This parameter must be a number between Min_Data = 2 and Max_Data = 15.
__PLLSAIR__	specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.

Note

the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices

Definition at line 6064 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG

#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG

(

__PLLI2SDivQ__

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))

Macro to configure the SAI clock Divider coming from PLLI2S.

Note

This function must be called before enabling the PLLI2S.

Parameters

__PLLI2SDivQ__

specifies the PLLI2S division factor for SAI1 clock. This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2SQ) / PLLI2SDivQ

Definition at line 6145 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG

#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG

(

__PLLSAIDivQ__

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))

Macro to configure the SAI clock Divider coming from PLLSAI.

Note

This function must be called before enabling the PLLSAI.

Parameters

__PLLSAIDivQ__

specifies the PLLSAI division factor for SAI1 clock . This parameter must be a number between Min_Data = 1 and Max_Data = 32. SAI1 clock frequency = f(PLLSAIQ) / PLLSAIDivQ

Definition at line 6153 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_SAI1_CONFIG

#define __HAL_RCC_SAI1_CONFIG

(

__SOURCE__

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))

Macro to configure SAI1 clock source selection.

Note

This configuration is only available with STM32F446xx Devices.

This function must be called before enabling PLL, PLLSAI, PLLI2S and the SAI clock.

Parameters

__SOURCE__

specifies the SAI1 clock source. This parameter can be one of the following values: RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.

Definition at line 6239 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_GET_SAI1_SOURCE

#define __HAL_RCC_GET_SAI1_SOURCE

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))

Macro to Get SAI1 clock source selection.

Note

This configuration is only available with STM32F446xx Devices.

Return values

The

clock source can be one of the following values: RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.

Definition at line 6249 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

__HAL_RCC_SAI2_CONFIG

#define __HAL_RCC_SAI2_CONFIG

(

__SOURCE__

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))

Macro to configure SAI2 clock source selection.

Note

This configuration is only available with STM32F446xx Devices.

This function must be called before enabling PLL, PLLSAI, PLLI2S and the SAI clock.

Parameters

__SOURCE__

specifies the SAI2 clock source. This parameter can be one of the following values: RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.

Definition at line 6262 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_GET_SAI2_SOURCE

#define __HAL_RCC_GET_SAI2_SOURCE

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))

Macro to Get SAI2 clock source selection.

Note

This configuration is only available with STM32F446xx Devices.

Return values

The

clock source can be one of the following values: RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.

Definition at line 6272 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

__HAL_RCC_I2S_APB1_CONFIG

#define __HAL_RCC_I2S_APB1_CONFIG

(

__SOURCE__

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))

Macro to configure I2S APB1 clock source selection.

Note

This function must be called before enabling PLL, PLLI2S and the I2S clock.

Parameters

__SOURCE__

specifies the I2S APB1 clock source. This parameter can be one of the following values: RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.

Definition at line 6283 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_GET_I2S_APB1_SOURCE

#define __HAL_RCC_GET_I2S_APB1_SOURCE

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))

Macro to Get I2S APB1 clock source selection.

Return values

The

clock source can be one of the following values: RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.

Definition at line 6292 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

__HAL_RCC_I2S_APB2_CONFIG

#define __HAL_RCC_I2S_APB2_CONFIG

(

__SOURCE__

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))

Macro to configure I2S APB2 clock source selection.

Note

This function must be called before enabling PLL, PLLI2S and the I2S clock.

Parameters

__SOURCE__

specifies the SAI Block A clock source. This parameter can be one of the following values: RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.

Definition at line 6303 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_GET_I2S_APB2_SOURCE

#define __HAL_RCC_GET_I2S_APB2_SOURCE

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))

Macro to Get I2S APB2 clock source selection.

Return values

The

clock source can be one of the following values: RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.

Definition at line 6312 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

__HAL_RCC_CEC_CONFIG

#define __HAL_RCC_CEC_CONFIG

(

__SOURCE__

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))

Macro to configure the CEC clock.

Parameters

__SOURCE__

specifies the CEC clock source. This parameter can be one of the following values: RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock

Definition at line 6320 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_GET_CEC_SOURCE

#define __HAL_RCC_GET_CEC_SOURCE

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))

Macro to Get the CEC clock.

Return values

The	clock source can be one of the following values: RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock

Definition at line 6327 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

__HAL_RCC_FMPI2C1_CONFIG

#define __HAL_RCC_FMPI2C1_CONFIG

(

__SOURCE__

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))

Macro to configure the FMPI2C1 clock.

Parameters

__SOURCE__

specifies the FMPI2C1 clock source. This parameter can be one of the following values: RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock

Definition at line 6336 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_GET_FMPI2C1_SOURCE

#define __HAL_RCC_GET_FMPI2C1_SOURCE

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))

Macro to Get the FMPI2C1 clock.

Return values

The	clock source can be one of the following values: RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock

Definition at line 6344 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

__HAL_RCC_CLK48_CONFIG

#define __HAL_RCC_CLK48_CONFIG

(

__SOURCE__

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))

Macro to configure the CLK48 clock.

Parameters

__SOURCE__

specifies the CLK48 clock source. This parameter can be one of the following values: RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.

Definition at line 6352 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_GET_CLK48_SOURCE

#define __HAL_RCC_GET_CLK48_SOURCE

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))

Macro to Get the CLK48 clock.

Return values

The	clock source can be one of the following values: RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.

Definition at line 6359 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

__HAL_RCC_SDIO_CONFIG

#define __HAL_RCC_SDIO_CONFIG

(

__SOURCE__

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))

Macro to configure the SDIO clock.

Parameters

__SOURCE__

specifies the SDIO clock source. This parameter can be one of the following values: RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.

Definition at line 6367 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_GET_SDIO_SOURCE

#define __HAL_RCC_GET_SDIO_SOURCE

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))

Macro to Get the SDIO clock.

Return values

The	clock source can be one of the following values: RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.

Definition at line 6374 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

__HAL_RCC_SPDIFRX_CONFIG

#define __HAL_RCC_SPDIFRX_CONFIG

(

__SOURCE__

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))

Macro to configure the SPDIFRX clock.

Parameters

__SOURCE__

specifies the SPDIFRX clock source. This parameter can be one of the following values: RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.

Definition at line 6382 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_GET_SPDIFRX_SOURCE

#define __HAL_RCC_GET_SPDIFRX_SOURCE

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))

Macro to Get the SPDIFRX clock.

Return values

The	clock source can be one of the following values: RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.

Definition at line 6389 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

__HAL_RCC_TIMCLKPRESCALER

#define __HAL_RCC_TIMCLKPRESCALER

(

__PRESC__

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))

Macro to configure the Timers clocks prescalers.

Note

This feature is only available with STM32F429x/439x Devices.

Parameters

__PRESC__

specifies the Timers clocks prescalers selection This parameter can be one of the following values: RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more. RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more.

Definition at line 6748 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

__HAL_RCC_PLLSAI_ENABLE_IT

#define __HAL_RCC_PLLSAI_ENABLE_IT

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))

Enable PLLSAI_RDY interrupt.

Definition at line 6759 of file stm32f4xx_hal_rcc_ex.h.

__HAL_RCC_PLLSAI_DISABLE_IT

#define __HAL_RCC_PLLSAI_DISABLE_IT

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))

Disable PLLSAI_RDY interrupt.

Definition at line 6763 of file stm32f4xx_hal_rcc_ex.h.

__HAL_RCC_PLLSAI_CLEAR_IT

#define __HAL_RCC_PLLSAI_CLEAR_IT

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

(RCC->CIR |= (RCC_CIR_PLLSAIRDYF))

Clear the PLLSAI RDY interrupt pending bits.

Definition at line 6767 of file stm32f4xx_hal_rcc_ex.h.

__HAL_RCC_PLLSAI_GET_IT

#define __HAL_RCC_PLLSAI_GET_IT

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))

Check the PLLSAI RDY interrupt has occurred or not.

Return values

The	new state (TRUE or FALSE).

Definition at line 6772 of file stm32f4xx_hal_rcc_ex.h.

__HAL_RCC_PLLSAI_GET_FLAG

#define __HAL_RCC_PLLSAI_GET_FLAG

(

)

#include <stm32f4xx_hal_rcc_ex.h>

Value:

((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))

Check PLLSAI RDY flag is set or not.

Return values

The	new state (TRUE or FALSE).

Definition at line 6777 of file stm32f4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().