STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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Macros
APB2 Peripheral Clock Enable Disable
STM32F4xx_HAL_Driver » RCCEx » RCCEx Exported Macros

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Collaboration diagram for APB2 Peripheral Clock Enable Disable:

Macros

#define __HAL_RCC_TIM8_CLK_ENABLE()
 
#define __HAL_RCC_ADC2_CLK_ENABLE()
 
#define __HAL_RCC_ADC3_CLK_ENABLE()
 
#define __HAL_RCC_SAI1_CLK_ENABLE()
 
#define __HAL_RCC_SAI2_CLK_ENABLE()
 
#define __HAL_RCC_SDIO_CLK_ENABLE()
 
#define __HAL_RCC_SPI4_CLK_ENABLE()
 
#define __HAL_RCC_TIM10_CLK_ENABLE()
 
#define __HAL_RCC_SDIO_CLK_DISABLE()
 
#define __HAL_RCC_SPI4_CLK_DISABLE()
 
#define __HAL_RCC_TIM10_CLK_DISABLE()
 
#define __HAL_RCC_TIM8_CLK_DISABLE()
 
#define __HAL_RCC_ADC2_CLK_DISABLE()
 
#define __HAL_RCC_ADC3_CLK_DISABLE()
 
#define __HAL_RCC_SAI1_CLK_DISABLE()
 
#define __HAL_RCC_SAI2_CLK_DISABLE()
 

Detailed Description

Enable or disable the High Speed APB (APB2) peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

◆ __HAL_RCC_TIM8_CLK_ENABLE

#define __HAL_RCC_TIM8_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 4383 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_ADC2_CLK_ENABLE

#define __HAL_RCC_ADC2_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 4390 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_ADC3_CLK_ENABLE

#define __HAL_RCC_ADC3_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 4397 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_SAI1_CLK_ENABLE

#define __HAL_RCC_SAI1_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 4404 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_SAI2_CLK_ENABLE

#define __HAL_RCC_SAI2_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 4411 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_SDIO_CLK_ENABLE

#define __HAL_RCC_SDIO_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 4418 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI4_CLK_ENABLE

#define __HAL_RCC_SPI4_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 4425 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM10_CLK_ENABLE

#define __HAL_RCC_TIM10_CLK_ENABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
UNUSED(tmpreg); \
} while(0U)

Definition at line 4432 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_SDIO_CLK_DISABLE

#define __HAL_RCC_SDIO_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))

Definition at line 4439 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_SPI4_CLK_DISABLE

#define __HAL_RCC_SPI4_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))

Definition at line 4440 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM10_CLK_DISABLE

#define __HAL_RCC_TIM10_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))

Definition at line 4441 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_TIM8_CLK_DISABLE

#define __HAL_RCC_TIM8_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))

Definition at line 4442 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_ADC2_CLK_DISABLE

#define __HAL_RCC_ADC2_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))

Definition at line 4443 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_ADC3_CLK_DISABLE

#define __HAL_RCC_ADC3_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))

Definition at line 4444 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_SAI1_CLK_DISABLE

#define __HAL_RCC_SAI1_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))

Definition at line 4445 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_SAI2_CLK_DISABLE

#define __HAL_RCC_SAI2_CLK_DISABLE ( )

#include <stm32f4xx_hal_rcc_ex.h>

Value:
(RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))

Definition at line 4446 of file stm32f4xx_hal_rcc_ex.h.