STM32F4xx HAL Documentation
Hardware Abstraction Layer for STM32F4 familiy
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stm32f4xx_hal_cryp.c
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1
257/* Includes ------------------------------------------------------------------*/
258#include "stm32f4xx_hal.h"
259
264#if defined (AES) || defined (CRYP)
265
272#ifdef HAL_CRYP_MODULE_ENABLED
273
274/* Private typedef -----------------------------------------------------------*/
275/* Private define ------------------------------------------------------------*/
279#define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
280#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
281#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
282
283#define CRYP_PHASE_READY 0x00000001U
284#define CRYP_PHASE_PROCESS 0x00000002U
286#if defined(AES)
287#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
288#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0
289#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1
290#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE
291#define CRYP_PHASE_INIT 0x00000000U
292#define CRYP_PHASE_HEADER AES_CR_GCMPH_0
293#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1
294#define CRYP_PHASE_FINAL AES_CR_GCMPH
295#else /* CRYP */
296#define CRYP_PHASE_INIT 0x00000000U
297#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
298#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
299#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
300#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
301#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
302#endif /* End CRYP or AES */
303
304/* CTR1 information to use in CCM algorithm */
305#define CRYP_CCM_CTR1_0 0x07FFFFFFU
306#define CRYP_CCM_CTR1_1 0xFFFFFF00U
307#define CRYP_CCM_CTR1_2 0x00000001U
308
309
315/* Private macro -------------------------------------------------------------*/
320#if defined(CRYP)
321
322#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
323 (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
324 }while(0)
325
326#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
327
328#else /*AES*/
329#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
330 (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
331 }while(0)
332#endif /* End AES or CRYP*/
333
334
339/* Private struct -------------------------------------------------------------*/
340/* Private variables ---------------------------------------------------------*/
341/* Private function prototypes -----------------------------------------------*/
346static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
347static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
348static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
349static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
350static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
351static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
352#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
353static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
354static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
355static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
356static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
357static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
358static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
359static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
360static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
361static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
362static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
363static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
364#endif /* AES or GCM CCM defined*/
365static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
366static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
367static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
368static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
369static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
370static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
371#if defined (CRYP)
372static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
373#if defined (CRYP_CR_ALGOMODE_AES_GCM)
374static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
375#endif /* GCM CCM defined*/
376static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
377static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
378static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
379#else /*AES*/
380static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
381#endif /* End CRYP or AES */
382
387/* Exported functions ---------------------------------------------------------*/
388
430HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
431{
432 /* Check the CRYP handle allocation */
433 if (hcryp == NULL)
434 {
435 return HAL_ERROR;
436 }
437
438 /* Check parameters */
439 assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
440 assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
441 assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
442 assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
443
444#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
445 if (hcryp->State == HAL_CRYP_STATE_RESET)
446 {
447 /* Allocate lock resource and initialize it */
448 hcryp->Lock = HAL_UNLOCKED;
449
450 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
451 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
452 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
453
454 if (hcryp->MspInitCallback == NULL)
455 {
456 hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
457 }
458
459 /* Init the low level hardware */
460 hcryp->MspInitCallback(hcryp);
461 }
462#else
463 if (hcryp->State == HAL_CRYP_STATE_RESET)
464 {
465 /* Allocate lock resource and initialize it */
466 hcryp->Lock = HAL_UNLOCKED;
467
468 /* Init the low level hardware */
469 HAL_CRYP_MspInit(hcryp);
470 }
471#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
472
473 /* Set the key size(This bit field is don't care in the DES or TDES modes) data type and Algorithm */
474#if defined (CRYP)
475
476 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
477 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
478
479#else /*AES*/
480
481 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
482 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
483
484#endif /* End AES or CRYP*/
485
486 /* Reset Error Code field */
487 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
488
489 /* Change the CRYP state */
490 hcryp->State = HAL_CRYP_STATE_READY;
491
492 /* Set the default CRYP phase */
493 hcryp->Phase = CRYP_PHASE_READY;
494
495 /* Return function status */
496 return HAL_OK;
497}
498
505HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
506{
507 /* Check the CRYP handle allocation */
508 if (hcryp == NULL)
509 {
510 return HAL_ERROR;
511 }
512
513 /* Set the default CRYP phase */
514 hcryp->Phase = CRYP_PHASE_READY;
515
516 /* Reset CrypInCount and CrypOutCount */
517 hcryp->CrypInCount = 0;
518 hcryp->CrypOutCount = 0;
519 hcryp->CrypHeaderCount = 0;
520
521 /* Disable the CRYP peripheral clock */
522 __HAL_CRYP_DISABLE(hcryp);
523
524#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
525
526 if (hcryp->MspDeInitCallback == NULL)
527 {
528 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
529 }
530 /* DeInit the low level hardware */
531 hcryp->MspDeInitCallback(hcryp);
532
533#else
534
535 /* DeInit the low level hardware: CLOCK, NVIC.*/
536 HAL_CRYP_MspDeInit(hcryp);
537
538#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
539
540 /* Change the CRYP state */
541 hcryp->State = HAL_CRYP_STATE_RESET;
542
543 /* Release Lock */
544 __HAL_UNLOCK(hcryp);
545
546 /* Return function status */
547 return HAL_OK;
548}
549
558HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
559{
560 /* Check the CRYP handle allocation */
561 if ((hcryp == NULL) || (pConf == NULL))
562 {
563 return HAL_ERROR;
564 }
565
566 /* Check parameters */
567 assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
568 assert_param(IS_CRYP_DATATYPE(pConf->DataType));
569 assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
570
571 if (hcryp->State == HAL_CRYP_STATE_READY)
572 {
573 /* Change the CRYP state */
574 hcryp->State = HAL_CRYP_STATE_BUSY;
575
576 /* Process locked */
577 __HAL_LOCK(hcryp);
578
579 /* Set CRYP parameters */
580 hcryp->Init.DataType = pConf->DataType;
581 hcryp->Init.pKey = pConf->pKey;
582 hcryp->Init.Algorithm = pConf->Algorithm;
583 hcryp->Init.KeySize = pConf->KeySize;
584 hcryp->Init.pInitVect = pConf->pInitVect;
585 hcryp->Init.Header = pConf->Header;
586 hcryp->Init.HeaderSize = pConf->HeaderSize;
587 hcryp->Init.B0 = pConf->B0;
588 hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
589 hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
590 hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
591
592 /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/
593#if defined (CRYP)
594
595 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
596 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
597
598#else /*AES*/
599 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
600 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
601
602 /*clear error flags*/
603 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
604
605#endif /* End AES or CRYP */
606
607 /* Process Unlocked */
608 __HAL_UNLOCK(hcryp);
609
610 /* Reset Error Code field */
611 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
612
613 /* Change the CRYP state */
614 hcryp->State = HAL_CRYP_STATE_READY;
615
616 /* Set the default CRYP phase */
617 hcryp->Phase = CRYP_PHASE_READY;
618
619 /* Return function status */
620 return HAL_OK;
621 }
622 else
623 {
624 /* Process Unlocked */
625 __HAL_UNLOCK(hcryp);
626
627 /* Busy error code field */
628 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
629 return HAL_ERROR;
630 }
631}
632
640HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
641{
642 /* Check the CRYP handle allocation */
643 if ((hcryp == NULL) || (pConf == NULL))
644 {
645 return HAL_ERROR;
646 }
647
648 if (hcryp->State == HAL_CRYP_STATE_READY)
649 {
650 /* Change the CRYP state */
651 hcryp->State = HAL_CRYP_STATE_BUSY;
652
653 /* Process locked */
654 __HAL_LOCK(hcryp);
655
656 /* Get CRYP parameters */
657 pConf->DataType = hcryp->Init.DataType;
658 pConf->pKey = hcryp->Init.pKey;
659 pConf->Algorithm = hcryp->Init.Algorithm;
660 pConf->KeySize = hcryp->Init.KeySize ;
661 pConf->pInitVect = hcryp->Init.pInitVect;
662 pConf->Header = hcryp->Init.Header ;
663 pConf->HeaderSize = hcryp->Init.HeaderSize;
664 pConf->B0 = hcryp->Init.B0;
665 pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
666 pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
667 pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
668
669 /* Process Unlocked */
670 __HAL_UNLOCK(hcryp);
671
672 /* Change the CRYP state */
673 hcryp->State = HAL_CRYP_STATE_READY;
674
675 /* Return function status */
676 return HAL_OK;
677 }
678 else
679 {
680 /* Process Unlocked */
681 __HAL_UNLOCK(hcryp);
682
683 /* Busy error code field */
684 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
685 return HAL_ERROR;
686 }
687}
694__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
695{
696 /* Prevent unused argument(s) compilation warning */
697 UNUSED(hcryp);
698
699 /* NOTE : This function should not be modified, when the callback is needed,
700 the HAL_CRYP_MspInit can be implemented in the user file
701 */
702}
703
710__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
711{
712 /* Prevent unused argument(s) compilation warning */
713 UNUSED(hcryp);
714
715 /* NOTE : This function should not be modified, when the callback is needed,
716 the HAL_CRYP_MspDeInit can be implemented in the user file
717 */
718}
719
720#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
735HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
736 pCRYP_CallbackTypeDef pCallback)
737{
738 HAL_StatusTypeDef status = HAL_OK;
739
740 if (pCallback == NULL)
741 {
742 /* Update the error code */
743 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
744
745 return HAL_ERROR;
746 }
747 /* Process locked */
748 __HAL_LOCK(hcryp);
749
750 if (hcryp->State == HAL_CRYP_STATE_READY)
751 {
752 switch (CallbackID)
753 {
754 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
755 hcryp->InCpltCallback = pCallback;
756 break;
757
758 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
759 hcryp->OutCpltCallback = pCallback;
760 break;
761
762 case HAL_CRYP_ERROR_CB_ID :
763 hcryp->ErrorCallback = pCallback;
764 break;
765
766 case HAL_CRYP_MSPINIT_CB_ID :
767 hcryp->MspInitCallback = pCallback;
768 break;
769
770 case HAL_CRYP_MSPDEINIT_CB_ID :
771 hcryp->MspDeInitCallback = pCallback;
772 break;
773
774 default :
775 /* Update the error code */
776 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
777 /* Return error status */
778 status = HAL_ERROR;
779 break;
780 }
781 }
782 else if (hcryp->State == HAL_CRYP_STATE_RESET)
783 {
784 switch (CallbackID)
785 {
786 case HAL_CRYP_MSPINIT_CB_ID :
787 hcryp->MspInitCallback = pCallback;
788 break;
789
790 case HAL_CRYP_MSPDEINIT_CB_ID :
791 hcryp->MspDeInitCallback = pCallback;
792 break;
793
794 default :
795 /* Update the error code */
796 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
797 /* Return error status */
798 status = HAL_ERROR;
799 break;
800 }
801 }
802 else
803 {
804 /* Update the error code */
805 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
806 /* Return error status */
807 status = HAL_ERROR;
808 }
809
810 /* Release Lock */
811 __HAL_UNLOCK(hcryp);
812
813 return status;
814}
815
829HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
830{
831 HAL_StatusTypeDef status = HAL_OK;
832
833 /* Process locked */
834 __HAL_LOCK(hcryp);
835
836 if (hcryp->State == HAL_CRYP_STATE_READY)
837 {
838 switch (CallbackID)
839 {
840 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
841 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
842 break;
843
844 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
845 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
846 break;
847
848 case HAL_CRYP_ERROR_CB_ID :
849 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
850 break;
851
852 case HAL_CRYP_MSPINIT_CB_ID :
853 hcryp->MspInitCallback = HAL_CRYP_MspInit;
854 break;
855
856 case HAL_CRYP_MSPDEINIT_CB_ID :
857 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
858 break;
859
860 default :
861 /* Update the error code */
862 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
863 /* Return error status */
864 status = HAL_ERROR;
865 break;
866 }
867 }
868 else if (hcryp->State == HAL_CRYP_STATE_RESET)
869 {
870 switch (CallbackID)
871 {
872 case HAL_CRYP_MSPINIT_CB_ID :
873 hcryp->MspInitCallback = HAL_CRYP_MspInit;
874 break;
875
876 case HAL_CRYP_MSPDEINIT_CB_ID :
877 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
878 break;
879
880 default :
881 /* Update the error code */
882 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
883 /* Return error status */
884 status = HAL_ERROR;
885 break;
886 }
887 }
888 else
889 {
890 /* Update the error code */
891 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
892 /* Return error status */
893 status = HAL_ERROR;
894 }
895
896 /* Release Lock */
897 __HAL_UNLOCK(hcryp);
898
899 return status;
900}
901#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
946HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
947 uint32_t Timeout)
948{
949 uint32_t algo;
950 HAL_StatusTypeDef status;
951
952 if (hcryp->State == HAL_CRYP_STATE_READY)
953 {
954 /* Change state Busy */
955 hcryp->State = HAL_CRYP_STATE_BUSY;
956
957 /* Process locked */
958 __HAL_LOCK(hcryp);
959
960 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
961 hcryp->CrypInCount = 0U;
962 hcryp->CrypOutCount = 0U;
963 hcryp->pCrypInBuffPtr = Input;
964 hcryp->pCrypOutBuffPtr = Output;
965
966 /* Calculate Size parameter in Byte*/
967 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
968 {
969 hcryp->Size = Size * 4U;
970 }
971 else
972 {
973 hcryp->Size = Size;
974 }
975
976#if defined (CRYP)
977 /* Set Encryption operating mode*/
978 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
979
980 /* algo get algorithm selected */
981 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
982
983 switch (algo)
984 {
985 case CRYP_DES_ECB:
986 case CRYP_DES_CBC:
987 case CRYP_TDES_ECB:
988 case CRYP_TDES_CBC:
989
990 /*Set Key */
991 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
992 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
993 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
994 {
995 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
996 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
997 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
998 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
999 }
1000
1001 /*Set Initialization Vector (IV)*/
1002 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1003 {
1004 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1005 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1006 }
1007
1008 /* Flush FIFO */
1009 HAL_CRYP_FIFO_FLUSH(hcryp);
1010
1011 /* Set the phase */
1012 hcryp->Phase = CRYP_PHASE_PROCESS;
1013
1014 /* Start DES/TDES encryption process */
1015 status = CRYP_TDES_Process(hcryp, Timeout);
1016 break;
1017
1018 case CRYP_AES_ECB:
1019 case CRYP_AES_CBC:
1020 case CRYP_AES_CTR:
1021
1022 /* AES encryption */
1023 status = CRYP_AES_Encrypt(hcryp, Timeout);
1024 break;
1025 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
1026 case CRYP_AES_GCM:
1027
1028 /* AES GCM encryption */
1029 status = CRYP_AESGCM_Process(hcryp, Timeout);
1030
1031 break;
1032
1033 case CRYP_AES_CCM:
1034
1035 /* AES CCM encryption */
1036 status = CRYP_AESCCM_Process(hcryp, Timeout);
1037 break;
1038 #endif /* GCM CCM defined*/
1039 default:
1040 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1041 /* Change the CRYP peripheral state */
1042 hcryp->State = HAL_CRYP_STATE_READY;
1043 /* Process unlocked */
1044 __HAL_UNLOCK(hcryp);
1045 return HAL_ERROR;
1046 }
1047
1048#else /*AES*/
1049
1050 /* Set the operating mode*/
1051 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1052
1053 /* algo get algorithm selected */
1054 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1055
1056 switch (algo)
1057 {
1058
1059 case CRYP_AES_ECB:
1060 case CRYP_AES_CBC:
1061 case CRYP_AES_CTR:
1062
1063 /* AES encryption */
1064 status = CRYP_AES_Encrypt(hcryp, Timeout);
1065 break;
1066
1067 case CRYP_AES_GCM_GMAC:
1068
1069 /* AES GCM encryption */
1070 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1071 break;
1072
1073 case CRYP_AES_CCM:
1074
1075 /* AES CCM encryption */
1076 status = CRYP_AESCCM_Process(hcryp, Timeout);
1077 break;
1078
1079 default:
1080 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1081 /* Change the CRYP peripheral state */
1082 hcryp->State = HAL_CRYP_STATE_READY;
1083 /* Process unlocked */
1084 __HAL_UNLOCK(hcryp);
1085 return HAL_ERROR;
1086 }
1087#endif /*end AES or CRYP */
1088
1089 if (status == HAL_OK)
1090 {
1091 /* Change the CRYP peripheral state */
1092 hcryp->State = HAL_CRYP_STATE_READY;
1093
1094 /* Process unlocked */
1095 __HAL_UNLOCK(hcryp);
1096 }
1097 }
1098 else
1099 {
1100 /* Busy error code field */
1101 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1102 return HAL_ERROR;
1103 }
1104
1105 /* Return function status */
1106 return HAL_OK;
1107}
1108
1119HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
1120 uint32_t Timeout)
1121{
1122 HAL_StatusTypeDef status;
1123 uint32_t algo;
1124
1125 if (hcryp->State == HAL_CRYP_STATE_READY)
1126 {
1127 /* Change state Busy */
1128 hcryp->State = HAL_CRYP_STATE_BUSY;
1129
1130 /* Process locked */
1131 __HAL_LOCK(hcryp);
1132
1133 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1134 hcryp->CrypInCount = 0U;
1135 hcryp->CrypOutCount = 0U;
1136 hcryp->pCrypInBuffPtr = Input;
1137 hcryp->pCrypOutBuffPtr = Output;
1138
1139 /* Calculate Size parameter in Byte*/
1140 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1141 {
1142 hcryp->Size = Size * 4U;
1143 }
1144 else
1145 {
1146 hcryp->Size = Size;
1147 }
1148
1149#if defined (CRYP)
1150
1151 /* Set Decryption operating mode*/
1152 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1153
1154 /* algo get algorithm selected */
1155 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1156
1157 switch (algo)
1158 {
1159 case CRYP_DES_ECB:
1160 case CRYP_DES_CBC:
1161 case CRYP_TDES_ECB:
1162 case CRYP_TDES_CBC:
1163
1164 /*Set Key */
1165 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1166 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1167 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1168 {
1169 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1170 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1171 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1172 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1173 }
1174
1175 /*Set Initialization Vector (IV)*/
1176 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1177 {
1178 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1179 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1180 }
1181
1182 /* Flush FIFO */
1183 HAL_CRYP_FIFO_FLUSH(hcryp);
1184
1185 /* Set the phase */
1186 hcryp->Phase = CRYP_PHASE_PROCESS;
1187
1188 /* Start DES/TDES decryption process */
1189 status = CRYP_TDES_Process(hcryp, Timeout);
1190
1191 break;
1192
1193 case CRYP_AES_ECB:
1194 case CRYP_AES_CBC:
1195 case CRYP_AES_CTR:
1196
1197 /* AES decryption */
1198 status = CRYP_AES_Decrypt(hcryp, Timeout);
1199 break;
1200 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
1201 case CRYP_AES_GCM:
1202
1203 /* AES GCM decryption */
1204 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1205 break;
1206
1207 case CRYP_AES_CCM:
1208
1209 /* AES CCM decryption */
1210 status = CRYP_AESCCM_Process(hcryp, Timeout);
1211 break;
1212 #endif /* GCM CCM defined*/
1213 default:
1214 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1215 /* Change the CRYP peripheral state */
1216 hcryp->State = HAL_CRYP_STATE_READY;
1217 /* Process unlocked */
1218 __HAL_UNLOCK(hcryp);
1219 return HAL_ERROR;
1220 }
1221
1222#else /*AES*/
1223
1224 /* Set Decryption operating mode*/
1225 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1226
1227 /* algo get algorithm selected */
1228 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1229
1230 switch (algo)
1231 {
1232
1233 case CRYP_AES_ECB:
1234 case CRYP_AES_CBC:
1235 case CRYP_AES_CTR:
1236
1237 /* AES decryption */
1238 status = CRYP_AES_Decrypt(hcryp, Timeout);
1239 break;
1240
1241 case CRYP_AES_GCM_GMAC:
1242
1243 /* AES GCM decryption */
1244 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1245 break;
1246
1247 case CRYP_AES_CCM:
1248
1249 /* AES CCM decryption */
1250 status = CRYP_AESCCM_Process(hcryp, Timeout);
1251 break;
1252
1253 default:
1254 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1255 /* Change the CRYP peripheral state */
1256 hcryp->State = HAL_CRYP_STATE_READY;
1257 /* Process unlocked */
1258 __HAL_UNLOCK(hcryp);
1259 return HAL_ERROR;
1260 }
1261#endif /* End AES or CRYP */
1262
1263 if (status == HAL_OK)
1264 {
1265 /* Change the CRYP peripheral state */
1266 hcryp->State = HAL_CRYP_STATE_READY;
1267
1268 /* Process unlocked */
1269 __HAL_UNLOCK(hcryp);
1270 }
1271 }
1272 else
1273 {
1274 /* Busy error code field */
1275 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1276 return HAL_ERROR;
1277 }
1278
1279 /* Return function status */
1280 return HAL_OK;
1281}
1282
1292HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1293{
1294 uint32_t algo;
1295 HAL_StatusTypeDef status = HAL_OK;
1296
1297 if (hcryp->State == HAL_CRYP_STATE_READY)
1298 {
1299 /* Change state Busy */
1300 hcryp->State = HAL_CRYP_STATE_BUSY;
1301
1302 /* Process locked */
1303 __HAL_LOCK(hcryp);
1304
1305 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1306 hcryp->CrypInCount = 0U;
1307 hcryp->CrypOutCount = 0U;
1308 hcryp->pCrypInBuffPtr = Input;
1309 hcryp->pCrypOutBuffPtr = Output;
1310
1311 /* Calculate Size parameter in Byte*/
1312 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1313 {
1314 hcryp->Size = Size * 4U;
1315 }
1316 else
1317 {
1318 hcryp->Size = Size;
1319 }
1320
1321#if defined (CRYP)
1322
1323 /* Set encryption operating mode*/
1324 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1325
1326 /* algo get algorithm selected */
1327 algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
1328
1329 switch (algo)
1330 {
1331 case CRYP_DES_ECB:
1332 case CRYP_DES_CBC:
1333 case CRYP_TDES_ECB:
1334 case CRYP_TDES_CBC:
1335
1336 /*Set Key */
1337 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1338 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1339 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1340 {
1341 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1342 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1343 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1344 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1345 }
1346 /* Set the Initialization Vector*/
1347 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1348 {
1349 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1350 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1351 }
1352
1353 /* Flush FIFO */
1354 HAL_CRYP_FIFO_FLUSH(hcryp);
1355
1356 /* Set the phase */
1357 hcryp->Phase = CRYP_PHASE_PROCESS;
1358
1359 /* Enable interrupts */
1360 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1361
1362 /* Enable CRYP to start DES/TDES process*/
1363 __HAL_CRYP_ENABLE(hcryp);
1364 break;
1365
1366 case CRYP_AES_ECB:
1367 case CRYP_AES_CBC:
1368 case CRYP_AES_CTR:
1369
1370 status = CRYP_AES_Encrypt_IT(hcryp);
1371 break;
1372 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
1373 case CRYP_AES_GCM:
1374
1375 status = CRYP_AESGCM_Process_IT(hcryp) ;
1376 break;
1377
1378 case CRYP_AES_CCM:
1379
1380 status = CRYP_AESCCM_Process_IT(hcryp);
1381 break;
1382 #endif /* GCM CCM defined*/
1383 default:
1384 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1385 /* Change the CRYP peripheral state */
1386 hcryp->State = HAL_CRYP_STATE_READY;
1387 /* Process unlocked */
1388 __HAL_UNLOCK(hcryp);
1389 status = HAL_ERROR;
1390 break;
1391 }
1392
1393#else /* AES */
1394
1395 /* Set encryption operating mode*/
1396 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1397
1398 /* algo get algorithm selected */
1399 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1400
1401 switch (algo)
1402 {
1403 case CRYP_AES_ECB:
1404 case CRYP_AES_CBC:
1405 case CRYP_AES_CTR:
1406
1407 /* AES encryption */
1408 status = CRYP_AES_Encrypt_IT(hcryp);
1409 break;
1410
1411 case CRYP_AES_GCM_GMAC:
1412
1413 /* AES GCM encryption */
1414 status = CRYP_AESGCM_Process_IT(hcryp) ;
1415 break;
1416
1417 case CRYP_AES_CCM:
1418
1419 /* AES CCM encryption */
1420 status = CRYP_AESCCM_Process_IT(hcryp);
1421 break;
1422
1423 default:
1424 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1425 /* Change the CRYP peripheral state */
1426 hcryp->State = HAL_CRYP_STATE_READY;
1427 /* Process unlocked */
1428 __HAL_UNLOCK(hcryp);
1429 status = HAL_ERROR;
1430 break;
1431 }
1432#endif /*end AES or CRYP*/
1433
1434 }
1435 else
1436 {
1437 /* Busy error code field */
1438 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1439 status = HAL_ERROR;
1440 }
1441
1442 /* Return function status */
1443 return status;
1444}
1445
1455HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1456{
1457 uint32_t algo;
1458 HAL_StatusTypeDef status = HAL_OK;
1459
1460 if (hcryp->State == HAL_CRYP_STATE_READY)
1461 {
1462 /* Change state Busy */
1463 hcryp->State = HAL_CRYP_STATE_BUSY;
1464
1465 /* Process locked */
1466 __HAL_LOCK(hcryp);
1467
1468 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1469 hcryp->CrypInCount = 0U;
1470 hcryp->CrypOutCount = 0U;
1471 hcryp->pCrypInBuffPtr = Input;
1472 hcryp->pCrypOutBuffPtr = Output;
1473
1474 /* Calculate Size parameter in Byte*/
1475 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1476 {
1477 hcryp->Size = Size * 4U;
1478 }
1479 else
1480 {
1481 hcryp->Size = Size;
1482 }
1483
1484#if defined (CRYP)
1485
1486 /* Set decryption operating mode*/
1487 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1488
1489 /* algo get algorithm selected */
1490 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1491
1492 switch (algo)
1493 {
1494 case CRYP_DES_ECB:
1495 case CRYP_DES_CBC:
1496 case CRYP_TDES_ECB:
1497 case CRYP_TDES_CBC:
1498
1499 /*Set Key */
1500 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1501 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1502 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1503 {
1504 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1505 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1506 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1507 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1508 }
1509
1510 /* Set the Initialization Vector*/
1511 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1512 {
1513 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1514 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1515 }
1516 /* Flush FIFO */
1517 HAL_CRYP_FIFO_FLUSH(hcryp);
1518
1519 /* Set the phase */
1520 hcryp->Phase = CRYP_PHASE_PROCESS;
1521
1522 /* Enable interrupts */
1523 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1524
1525 /* Enable CRYP and start DES/TDES process*/
1526 __HAL_CRYP_ENABLE(hcryp);
1527
1528 break;
1529
1530 case CRYP_AES_ECB:
1531 case CRYP_AES_CBC:
1532 case CRYP_AES_CTR:
1533
1534 /* AES decryption */
1535 status = CRYP_AES_Decrypt_IT(hcryp);
1536 break;
1537 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
1538 case CRYP_AES_GCM:
1539
1540 /* AES GCM decryption */
1541 status = CRYP_AESGCM_Process_IT(hcryp) ;
1542 break;
1543
1544 case CRYP_AES_CCM:
1545
1546 /* AES CCMdecryption */
1547 status = CRYP_AESCCM_Process_IT(hcryp);
1548 break;
1549 #endif /* GCM CCM defined*/
1550 default:
1551 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1552 /* Change the CRYP peripheral state */
1553 hcryp->State = HAL_CRYP_STATE_READY;
1554 /* Process unlocked */
1555 __HAL_UNLOCK(hcryp);
1556 status = HAL_ERROR;
1557 break;
1558 }
1559
1560#else /*AES*/
1561
1562 /* Set decryption operating mode*/
1563 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1564
1565 /* algo get algorithm selected */
1566 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1567
1568 switch (algo)
1569 {
1570 case CRYP_AES_ECB:
1571 case CRYP_AES_CBC:
1572 case CRYP_AES_CTR:
1573
1574 /* AES decryption */
1575 status = CRYP_AES_Decrypt_IT(hcryp);
1576 break;
1577
1578 case CRYP_AES_GCM_GMAC:
1579
1580 /* AES GCM decryption */
1581 status = CRYP_AESGCM_Process_IT(hcryp) ;
1582 break;
1583
1584 case CRYP_AES_CCM:
1585
1586 /* AES CCM decryption */
1587 status = CRYP_AESCCM_Process_IT(hcryp);
1588 break;
1589
1590 default:
1591 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1592 /* Change the CRYP peripheral state */
1593 hcryp->State = HAL_CRYP_STATE_READY;
1594 /* Process unlocked */
1595 __HAL_UNLOCK(hcryp);
1596 status = HAL_ERROR;
1597 break;
1598 }
1599#endif /* End AES or CRYP */
1600
1601 }
1602 else
1603 {
1604 /* Busy error code field */
1605 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1606 status = HAL_ERROR;
1607 }
1608
1609 /* Return function status */
1610 return status;
1611}
1612
1622HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1623{
1624 uint32_t algo;
1625 HAL_StatusTypeDef status = HAL_OK;
1626 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
1627
1628 if (hcryp->State == HAL_CRYP_STATE_READY)
1629 {
1630 /* Change state Busy */
1631 hcryp->State = HAL_CRYP_STATE_BUSY;
1632
1633 /* Process locked */
1634 __HAL_LOCK(hcryp);
1635
1636 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1637 hcryp->CrypInCount = 0U;
1638 hcryp->CrypOutCount = 0U;
1639 hcryp->pCrypInBuffPtr = Input;
1640 hcryp->pCrypOutBuffPtr = Output;
1641
1642 /* Calculate Size parameter in Byte*/
1643 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1644 {
1645 hcryp->Size = Size * 4U;
1646 }
1647 else
1648 {
1649 hcryp->Size = Size;
1650 }
1651
1652#if defined (CRYP)
1653
1654 /* Set encryption operating mode*/
1655 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1656
1657 /* algo get algorithm selected */
1658 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1659
1660 switch (algo)
1661 {
1662 case CRYP_DES_ECB:
1663 case CRYP_DES_CBC:
1664 case CRYP_TDES_ECB:
1665 case CRYP_TDES_CBC:
1666
1667 /*Set Key */
1668 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1669 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1670 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1671 {
1672 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1673 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1674 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1675 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1676 }
1677
1678 /* Set the Initialization Vector*/
1679 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1680 {
1681 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1682 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1683 }
1684
1685 /* Flush FIFO */
1686 HAL_CRYP_FIFO_FLUSH(hcryp);
1687
1688 /* Set the phase */
1689 hcryp->Phase = CRYP_PHASE_PROCESS;
1690
1691 /* Start DMA process transfer for DES/TDES */
1692 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1693 (uint32_t)(hcryp->pCrypOutBuffPtr));
1694 break;
1695
1696 case CRYP_AES_ECB:
1697 case CRYP_AES_CBC:
1698 case CRYP_AES_CTR:
1699
1700 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1701 {
1702 if (hcryp->KeyIVConfig == 1U)
1703 {
1704 /* If the Key and IV configuration has to be done only once
1705 and if it has already been done, skip it */
1706 DoKeyIVConfig = 0U;
1707 }
1708 else
1709 {
1710 /* If the Key and IV configuration has to be done only once
1711 and if it has not been done already, do it and set KeyIVConfig
1712 to keep track it won't have to be done again next time */
1713 hcryp->KeyIVConfig = 1U;
1714 }
1715 }
1716
1717 if (DoKeyIVConfig == 1U)
1718 {
1719 /* Set the Key*/
1720 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1721
1722 /* Set the Initialization Vector*/
1723 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1724 {
1725 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1726 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
1727 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
1728 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
1729 }
1730 } /* if (DoKeyIVConfig == 1U) */
1731
1732 /* Set the phase */
1733 hcryp->Phase = CRYP_PHASE_PROCESS;
1734
1735 /* Start DMA process transfer for AES */
1736 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1737 (uint32_t)(hcryp->pCrypOutBuffPtr));
1738 break;
1739 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
1740 case CRYP_AES_GCM:
1741 /* AES GCM encryption */
1742 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1743 break;
1744
1745 case CRYP_AES_CCM:
1746 /* AES CCM encryption */
1747 status = CRYP_AESCCM_Process_DMA(hcryp);
1748 break;
1749 #endif /* GCM CCM defined*/
1750 default:
1751 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1752 /* Change the CRYP peripheral state */
1753 hcryp->State = HAL_CRYP_STATE_READY;
1754 /* Process unlocked */
1755 __HAL_UNLOCK(hcryp);
1756 status = HAL_ERROR;
1757 break;
1758 }
1759
1760#else /*AES*/
1761 /* Set encryption operating mode*/
1762 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1763
1764 /* algo get algorithm selected */
1765 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1766
1767 switch (algo)
1768 {
1769
1770 case CRYP_AES_ECB:
1771 case CRYP_AES_CBC:
1772 case CRYP_AES_CTR:
1773
1774 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1775 {
1776 if (hcryp->KeyIVConfig == 1U)
1777 {
1778 /* If the Key and IV configuration has to be done only once
1779 and if it has already been done, skip it */
1780 DoKeyIVConfig = 0U;
1781 }
1782 else
1783 {
1784 /* If the Key and IV configuration has to be done only once
1785 and if it has not been done already, do it and set KeyIVConfig
1786 to keep track it won't have to be done again next time */
1787 hcryp->KeyIVConfig = 1U;
1788 }
1789 }
1790
1791 if (DoKeyIVConfig == 1U)
1792 {
1793 /* Set the Key*/
1794 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1795
1796 /* Set the Initialization Vector*/
1797 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1798 {
1799 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
1800 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1801 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
1802 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
1803 }
1804 } /* if (DoKeyIVConfig == 1U) */
1805 /* Set the phase */
1806 hcryp->Phase = CRYP_PHASE_PROCESS;
1807
1808 /* Start DMA process transfer for AES */
1809 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1810 break;
1811
1812 case CRYP_AES_GCM_GMAC:
1813 /* AES GCM encryption */
1814 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1815 break;
1816
1817 case CRYP_AES_CCM:
1818 /* AES CCM encryption */
1819 status = CRYP_AESCCM_Process_DMA(hcryp);
1820 break;
1821
1822 default:
1823 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1824 /* Change the CRYP peripheral state */
1825 hcryp->State = HAL_CRYP_STATE_READY;
1826 /* Process unlocked */
1827 __HAL_UNLOCK(hcryp);
1828 status = HAL_ERROR;
1829 break;
1830 }
1831#endif /* End AES or CRYP */
1832
1833 }
1834 else
1835 {
1836 /* Busy error code field */
1837 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1838 status = HAL_ERROR;
1839 }
1840
1841 /* Return function status */
1842 return status;
1843}
1844
1854HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1855{
1856 uint32_t algo;
1857 HAL_StatusTypeDef status = HAL_OK;
1858
1859 if (hcryp->State == HAL_CRYP_STATE_READY)
1860 {
1861
1862 /* Change state Busy */
1863 hcryp->State = HAL_CRYP_STATE_BUSY;
1864
1865 /* Process locked */
1866 __HAL_LOCK(hcryp);
1867
1868 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1869 hcryp->CrypInCount = 0U;
1870 hcryp->CrypOutCount = 0U;
1871 hcryp->pCrypInBuffPtr = Input;
1872 hcryp->pCrypOutBuffPtr = Output;
1873
1874 /* Calculate Size parameter in Byte*/
1875 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1876 {
1877 hcryp->Size = Size * 4U;
1878 }
1879 else
1880 {
1881 hcryp->Size = Size;
1882 }
1883
1884#if defined (CRYP)
1885
1886 /* Set decryption operating mode*/
1887 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1888
1889 /* algo get algorithm selected */
1890 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1891
1892 switch (algo)
1893 {
1894 case CRYP_DES_ECB:
1895 case CRYP_DES_CBC:
1896 case CRYP_TDES_ECB:
1897 case CRYP_TDES_CBC:
1898
1899 /*Set Key */
1900 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1901 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1902 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1903 {
1904 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1905 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1906 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1907 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1908 }
1909
1910 /* Set the Initialization Vector*/
1911 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1912 {
1913 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1914 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1915 }
1916
1917 /* Flush FIFO */
1918 HAL_CRYP_FIFO_FLUSH(hcryp);
1919
1920 /* Set the phase */
1921 hcryp->Phase = CRYP_PHASE_PROCESS;
1922
1923 /* Start DMA process transfer for DES/TDES */
1924 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1925 (uint32_t)(hcryp->pCrypOutBuffPtr));
1926 break;
1927
1928 case CRYP_AES_ECB:
1929 case CRYP_AES_CBC:
1930 case CRYP_AES_CTR:
1931
1932 /* AES decryption */
1933 status = CRYP_AES_Decrypt_DMA(hcryp);
1934 break;
1935 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
1936 case CRYP_AES_GCM:
1937 /* AES GCM decryption */
1938 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1939 break;
1940
1941 case CRYP_AES_CCM:
1942 /* AES CCM decryption */
1943 status = CRYP_AESCCM_Process_DMA(hcryp);
1944 break;
1945 #endif /* GCM CCM defined*/
1946 default:
1947 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1948 /* Change the CRYP peripheral state */
1949 hcryp->State = HAL_CRYP_STATE_READY;
1950 /* Process unlocked */
1951 __HAL_UNLOCK(hcryp);
1952 status = HAL_ERROR;
1953 break;
1954 }
1955
1956#else /*AES*/
1957
1958 /* Set decryption operating mode*/
1959 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1960
1961 /* algo get algorithm selected */
1962 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1963
1964 switch (algo)
1965 {
1966
1967 case CRYP_AES_ECB:
1968 case CRYP_AES_CBC:
1969 case CRYP_AES_CTR:
1970
1971 /* AES decryption */
1972 status = CRYP_AES_Decrypt_DMA(hcryp);
1973 break;
1974
1975 case CRYP_AES_GCM_GMAC:
1976 /* AES GCM decryption */
1977 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1978 break;
1979
1980 case CRYP_AES_CCM:
1981 /* AES CCM decryption */
1982 status = CRYP_AESCCM_Process_DMA(hcryp);
1983 break;
1984
1985 default:
1986 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1987 /* Change the CRYP peripheral state */
1988 hcryp->State = HAL_CRYP_STATE_READY;
1989 /* Process unlocked */
1990 __HAL_UNLOCK(hcryp);
1991 status = HAL_ERROR;
1992 break;
1993 }
1994#endif /* End AES or CRYP */
1995 }
1996 else
1997 {
1998 /* Busy error code field */
1999 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2000 status = HAL_ERROR;
2001 }
2002
2003 /* Return function status */
2004 return status;
2005}
2006
2035void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
2036{
2037
2038#if defined (CRYP)
2039
2040 uint32_t itstatus = hcryp->Instance->MISR;
2041
2042 if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U)
2043 {
2044 if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC)
2045 || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
2046 {
2047 CRYP_TDES_IT(hcryp); /* DES or TDES*/
2048 }
2049 else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC)
2050 || (hcryp->Init.Algorithm == CRYP_AES_CTR))
2051 {
2052 CRYP_AES_IT(hcryp); /*AES*/
2053 }
2054 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
2055 else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM))
2056 {
2057 /* if header phase */
2058 if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2059 {
2060 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2061 }
2062 else /* if payload phase */
2063 {
2064 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2065 }
2066 }
2067 #endif /* GCM CCM defined*/
2068 else
2069 {
2070 /* Nothing to do */
2071 }
2072 }
2073
2074#else /*AES*/
2075 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET)
2076 {
2077 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
2078 {
2079
2080 /* Clear computation complete flag */
2081 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2082
2083 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
2084 {
2085
2086 /* if header phase */
2087 if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2088 {
2089 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2090 }
2091 else /* if payload phase */
2092 {
2093 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2094 }
2095 }
2096 else if (hcryp->Init.Algorithm == CRYP_AES_CCM)
2097 {
2098 /* if header phase */
2099 if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount)
2100 {
2101 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2102 }
2103 else /* if payload phase */
2104 {
2105 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2106 }
2107 }
2108 else /* AES Algorithm ECB,CBC or CTR*/
2109 {
2110 CRYP_AES_IT(hcryp);
2111 }
2112 }
2113 }
2114 /* Check if error occurred */
2115 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET)
2116 {
2117 /* If write Error occurred */
2118 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET)
2119 {
2120 hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
2121 }
2122 /* If read Error occurred */
2123 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET)
2124 {
2125 hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
2126 }
2127 }
2128#endif /* End AES or CRYP */
2129}
2130
2137uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
2138{
2139 return hcryp->ErrorCode;
2140}
2141
2148HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
2149{
2150 return hcryp->State;
2151}
2152
2159__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
2160{
2161 /* Prevent unused argument(s) compilation warning */
2162 UNUSED(hcryp);
2163
2164 /* NOTE : This function should not be modified, when the callback is needed,
2165 the HAL_CRYP_InCpltCallback can be implemented in the user file
2166 */
2167}
2168
2175__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
2176{
2177 /* Prevent unused argument(s) compilation warning */
2178 UNUSED(hcryp);
2179
2180 /* NOTE : This function should not be modified, when the callback is needed,
2181 the HAL_CRYP_OutCpltCallback can be implemented in the user file
2182 */
2183}
2184
2191__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
2192{
2193 /* Prevent unused argument(s) compilation warning */
2194 UNUSED(hcryp);
2195
2196 /* NOTE : This function Should not be modified, when the callback is needed,
2197 the HAL_CRYP_ErrorCallback could be implemented in the user file
2198 */
2199}
2204/* Private functions ---------------------------------------------------------*/
2209#if defined (CRYP)
2210
2218static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2219{
2220 uint32_t temp[2]; /* Temporary CrypOutBuff */
2221 uint16_t incount; /* Temporary CrypInCount Value */
2222 uint16_t outcount; /* Temporary CrypOutCount Value */
2223 uint32_t i;
2224
2225 /* Enable CRYP */
2226 __HAL_CRYP_ENABLE(hcryp);
2227 /*Temporary CrypOutCount Value*/
2228 outcount = hcryp->CrypOutCount;
2229
2230 /*Start processing*/
2231 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2232 {
2233 /* Temporary CrypInCount Value */
2234 incount = hcryp->CrypInCount;
2235 /* Write plain data and get cipher data */
2236 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
2237 {
2238 /* Write the input block in the IN FIFO */
2239 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2240 hcryp->CrypInCount++;
2241 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2242 hcryp->CrypInCount++;
2243 }
2244
2245 /* Wait for OFNE flag to be raised */
2246 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
2247 {
2248 /* Disable the CRYP peripheral clock */
2249 __HAL_CRYP_DISABLE(hcryp);
2250
2251 /* Change state & errorCode*/
2252 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2253 hcryp->State = HAL_CRYP_STATE_READY;
2254
2255 /* Process unlocked */
2256 __HAL_UNLOCK(hcryp);
2257#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2258 /*Call registered error callback*/
2259 hcryp->ErrorCallback(hcryp);
2260#else
2261 /*Call legacy weak error callback*/
2262 HAL_CRYP_ErrorCallback(hcryp);
2263#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2264 }
2265
2266 /*Temporary CrypOutCount Value*/
2267 outcount = hcryp->CrypOutCount;
2268
2269 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
2270 {
2271 /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
2272 for (i = 0U; i < 2U; i++)
2273 {
2274 temp[i] = hcryp->Instance->DOUT;
2275 }
2276 i = 0U;
2277 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
2278 {
2279 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
2280 hcryp->CrypOutCount++;
2281 i++;
2282 }
2283 }
2284 /*Temporary CrypOutCount Value*/
2285 outcount = hcryp->CrypOutCount;
2286 }
2287 /* Disable CRYP */
2288 __HAL_CRYP_DISABLE(hcryp);
2289 /* Change the CRYP state */
2290 hcryp->State = HAL_CRYP_STATE_READY;
2291
2292 /* Return function status */
2293 return HAL_OK;
2294}
2295
2304static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
2305{
2306 uint32_t temp[2]; /* Temporary CrypOutBuff */
2307 uint32_t i;
2308
2309 if (hcryp->State == HAL_CRYP_STATE_BUSY)
2310 {
2311 if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U)
2312 {
2313 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)
2314 {
2315 /* Write input block in the IN FIFO */
2316 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2317 hcryp->CrypInCount++;
2318 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2319 hcryp->CrypInCount++;
2320
2321 if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
2322 {
2323 /* Disable interruption */
2324 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
2325 /* Call the input data transfer complete callback */
2326#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
2327 /*Call registered Input complete callback*/
2328 hcryp->InCpltCallback(hcryp);
2329#else
2330 /*Call legacy weak Input complete callback*/
2331 HAL_CRYP_InCpltCallback(hcryp);
2332#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2333 }
2334 }
2335 }
2336 if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)
2337 {
2338 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)
2339 {
2340 /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
2341 for (i = 0U; i < 2U; i++)
2342 {
2343 temp[i] = hcryp->Instance->DOUT;
2344 }
2345 i = 0U;
2346 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
2347 {
2348 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
2349 hcryp->CrypOutCount++;
2350 i++;
2351 }
2352 if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
2353 {
2354 /* Disable interruption */
2355 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
2356
2357 /* Disable CRYP */
2358 __HAL_CRYP_DISABLE(hcryp);
2359
2360 /* Process unlocked */
2361 __HAL_UNLOCK(hcryp);
2362
2363 /* Change the CRYP state */
2364 hcryp->State = HAL_CRYP_STATE_READY;
2365 /* Call output transfer complete callback */
2366#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2367 /*Call registered Output complete callback*/
2368 hcryp->OutCpltCallback(hcryp);
2369#else
2370 /*Call legacy weak Output complete callback*/
2371 HAL_CRYP_OutCpltCallback(hcryp);
2372#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2373 }
2374 }
2375 }
2376 }
2377 else
2378 {
2379 /* Process unlocked */
2380 __HAL_UNLOCK(hcryp);
2381 /* Busy error code field */
2382 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2383#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2384 /*Call registered error callback*/
2385 hcryp->ErrorCallback(hcryp);
2386#else
2387 /*Call legacy weak error callback*/
2388 HAL_CRYP_ErrorCallback(hcryp);
2389#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2390 }
2391}
2392
2393#endif /* CRYP */
2394
2401static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2402{
2403 uint16_t outcount; /* Temporary CrypOutCount Value */
2404 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2405
2406 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2407 {
2408 if (hcryp->KeyIVConfig == 1U)
2409 {
2410 /* If the Key and IV configuration has to be done only once
2411 and if it has already been done, skip it */
2412 DoKeyIVConfig = 0U;
2413 }
2414 else
2415 {
2416 /* If the Key and IV configuration has to be done only once
2417 and if it has not been done already, do it and set KeyIVConfig
2418 to keep track it won't have to be done again next time */
2419 hcryp->KeyIVConfig = 1U;
2420 }
2421 }
2422
2423 if (DoKeyIVConfig == 1U)
2424 {
2425
2426 /* Set the Key*/
2427 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2428
2429 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2430 {
2431 /* Set the Initialization Vector*/
2432#if defined (AES)
2433 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2434 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2435 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2436 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2437#else /* CRYP */
2438 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2439 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2440 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2441 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2442#endif /* End AES or CRYP */
2443 }
2444 } /* if (DoKeyIVConfig == 1U) */
2445
2446 /* Set the phase */
2447 hcryp->Phase = CRYP_PHASE_PROCESS;
2448
2449 /* Enable CRYP */
2450 __HAL_CRYP_ENABLE(hcryp);
2451
2452 /*Temporary CrypOutCount Value*/
2453 outcount = hcryp->CrypOutCount;
2454
2455 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2456 {
2457 /* Write plain Ddta and get cipher data */
2458 CRYP_AES_ProcessData(hcryp, Timeout);
2459 /*Temporary CrypOutCount Value*/
2460 outcount = hcryp->CrypOutCount;
2461 }
2462
2463 /* Disable CRYP */
2464 __HAL_CRYP_DISABLE(hcryp);
2465
2466 /* Change the CRYP state */
2467 hcryp->State = HAL_CRYP_STATE_READY;
2468
2469 /* Return function status */
2470 return HAL_OK;
2471}
2472
2479static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
2480{
2481 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2482
2483 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2484 {
2485 if (hcryp->KeyIVConfig == 1U)
2486 {
2487 /* If the Key and IV configuration has to be done only once
2488 and if it has already been done, skip it */
2489 DoKeyIVConfig = 0U;
2490 }
2491 else
2492 {
2493 /* If the Key and IV configuration has to be done only once
2494 and if it has not been done already, do it and set KeyIVConfig
2495 to keep track it won't have to be done again next time */
2496 hcryp->KeyIVConfig = 1U;
2497 }
2498 }
2499
2500 if (DoKeyIVConfig == 1U)
2501 {
2502 /* Set the Key*/
2503 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2504
2505 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2506 {
2507 /* Set the Initialization Vector*/
2508#if defined (AES)
2509 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2510 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2511 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2512 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2513
2514#else /* CRYP */
2515 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2516 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2517 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2518 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2519#endif /* End AES or CRYP */
2520 }
2521 } /* if (DoKeyIVConfig == 1U) */
2522
2523 /* Set the phase */
2524 hcryp->Phase = CRYP_PHASE_PROCESS;
2525
2526 if (hcryp->Size != 0U)
2527 {
2528#if defined (AES)
2529
2530 /* Enable computation complete flag and error interrupts */
2531 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
2532
2533 /* Enable CRYP */
2534 __HAL_CRYP_ENABLE(hcryp);
2535
2536 /* Increment the pointer before writing the input block in the IN FIFO to make sure that
2537 when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
2538 and it is ready for the next operation. */
2539 hcryp->CrypInCount++;
2540 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2541 hcryp->CrypInCount++;
2542 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2543 hcryp->CrypInCount++;
2544 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2545 hcryp->CrypInCount++;
2546 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2547
2548#else /* CRYP */
2549
2550 /* Enable interrupts */
2551 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2552
2553 /* Enable CRYP */
2554 __HAL_CRYP_ENABLE(hcryp);
2555
2556#endif /* End AES or CRYP */
2557 }
2558 else
2559 {
2560 /* Change the CRYP state */
2561 hcryp->State = HAL_CRYP_STATE_READY;
2562
2563 /* Process unlocked */
2564 __HAL_UNLOCK(hcryp);
2565 }
2566
2567 /* Return function status */
2568 return HAL_OK;
2569}
2570
2577static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2578{
2579 uint16_t outcount; /* Temporary CrypOutCount Value */
2580 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2581
2582 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2583 {
2584 if (hcryp->KeyIVConfig == 1U)
2585 {
2586 /* If the Key and IV configuration has to be done only once
2587 and if it has already been done, skip it */
2588 DoKeyIVConfig = 0U;
2589 }
2590 else
2591 {
2592 /* If the Key and IV configuration has to be done only once
2593 and if it has not been done already, do it and set KeyIVConfig
2594 to keep track it won't have to be done again next time */
2595 hcryp->KeyIVConfig = 1U;
2596 }
2597 }
2598
2599 if (DoKeyIVConfig == 1U)
2600 {
2601 /* Key preparation for ECB/CBC */
2602 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2603 {
2604#if defined (AES)
2605 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
2606 {
2607 /* Set key preparation for decryption operating mode*/
2608 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2609
2610 /* Set the Key*/
2611 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2612
2613 /* Enable CRYP */
2614 __HAL_CRYP_ENABLE(hcryp);
2615
2616 /* Wait for CCF flag to be raised */
2617 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
2618 {
2619 /* Disable the CRYP peripheral clock */
2620 __HAL_CRYP_DISABLE(hcryp);
2621
2622 /* Change state & error code*/
2623 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2624 hcryp->State = HAL_CRYP_STATE_READY;
2625
2626 /* Process unlocked */
2627 __HAL_UNLOCK(hcryp);
2628 return HAL_ERROR;
2629 }
2630 /* Clear CCF Flag */
2631 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2632
2633 /* Return to decryption operating mode(Mode 3)*/
2634 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2635 }
2636 else /*Mode 4 : decryption & Key preparation*/
2637 {
2638 /* Set the Key*/
2639 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2640
2641 /* Set decryption & Key preparation operating mode*/
2642 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2643 }
2644#else /* CRYP */
2645 /* change ALGOMODE to key preparation for decryption*/
2646 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2647
2648 /* Set the Key*/
2649 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2650
2651 /* Enable CRYP */
2652 __HAL_CRYP_ENABLE(hcryp);
2653
2654 /* Wait for BUSY flag to be raised */
2655 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
2656 {
2657 /* Disable the CRYP peripheral clock */
2658 __HAL_CRYP_DISABLE(hcryp);
2659
2660 /* Change state */
2661 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2662 hcryp->State = HAL_CRYP_STATE_READY;
2663
2664 /* Process unlocked */
2665 __HAL_UNLOCK(hcryp);
2666 return HAL_ERROR;
2667 }
2668 /* Turn back to ALGOMODE of the configuration */
2669 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2670
2671#endif /* End AES or CRYP */
2672 }
2673 else /*Algorithm CTR */
2674 {
2675 /* Set the Key*/
2676 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2677 }
2678
2679 /* Set IV */
2680 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2681 {
2682 /* Set the Initialization Vector*/
2683#if defined (AES)
2684 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2685 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2686 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2687 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2688#else /* CRYP */
2689 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2690 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2691 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2692 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2693#endif /* End AES or CRYP */
2694 }
2695 } /* if (DoKeyIVConfig == 1U) */
2696 /* Set the phase */
2697 hcryp->Phase = CRYP_PHASE_PROCESS;
2698
2699 /* Enable CRYP */
2700 __HAL_CRYP_ENABLE(hcryp);
2701
2702 /*Temporary CrypOutCount Value*/
2703 outcount = hcryp->CrypOutCount;
2704
2705 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2706 {
2707 /* Write plain data and get cipher data */
2708 CRYP_AES_ProcessData(hcryp, Timeout);
2709 /*Temporary CrypOutCount Value*/
2710 outcount = hcryp->CrypOutCount;
2711 }
2712
2713 /* Disable CRYP */
2714 __HAL_CRYP_DISABLE(hcryp);
2715
2716 /* Change the CRYP state */
2717 hcryp->State = HAL_CRYP_STATE_READY;
2718
2719 /* Return function status */
2720 return HAL_OK;
2721}
2728static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
2729{
2730 __IO uint32_t count = 0U;
2731 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2732
2733 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2734 {
2735 if (hcryp->KeyIVConfig == 1U)
2736 {
2737 /* If the Key and IV configuration has to be done only once
2738 and if it has already been done, skip it */
2739 DoKeyIVConfig = 0U;
2740 }
2741 else
2742 {
2743 /* If the Key and IV configuration has to be done only once
2744 and if it has not been done already, do it and set KeyIVConfig
2745 to keep track it won't have to be done again next time */
2746 hcryp->KeyIVConfig = 1U;
2747 }
2748 }
2749
2750 if (DoKeyIVConfig == 1U)
2751 {
2752 /* Key preparation for ECB/CBC */
2753 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2754 {
2755#if defined (AES)
2756 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
2757 {
2758 /* Set key preparation for decryption operating mode*/
2759 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2760
2761 /* Set the Key*/
2762 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2763
2764 /* Enable CRYP */
2765 __HAL_CRYP_ENABLE(hcryp);
2766
2767 /* Wait for CCF flag to be raised */
2768 count = CRYP_TIMEOUT_KEYPREPARATION;
2769 do
2770 {
2771 count-- ;
2772 if (count == 0U)
2773 {
2774 /* Disable the CRYP peripheral clock */
2775 __HAL_CRYP_DISABLE(hcryp);
2776
2777 /* Change state */
2778 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2779 hcryp->State = HAL_CRYP_STATE_READY;
2780
2781 /* Process unlocked */
2782 __HAL_UNLOCK(hcryp);
2783 return HAL_ERROR;
2784 }
2785 }
2786 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2787
2788 /* Clear CCF Flag */
2789 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2790
2791 /* Return to decryption operating mode(Mode 3)*/
2792 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2793 }
2794 else /*Mode 4 : decryption & key preparation*/
2795 {
2796 /* Set the Key*/
2797 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2798
2799 /* Set decryption & key preparation operating mode*/
2800 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2801 }
2802#else /* CRYP */
2803
2804 /* change ALGOMODE to key preparation for decryption*/
2805 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2806
2807 /* Set the Key*/
2808 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2809
2810 /* Enable CRYP */
2811 __HAL_CRYP_ENABLE(hcryp);
2812
2813 /* Wait for BUSY flag to be raised */
2814 count = CRYP_TIMEOUT_KEYPREPARATION;
2815 do
2816 {
2817 count-- ;
2818 if (count == 0U)
2819 {
2820 /* Change state */
2821 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2822 hcryp->State = HAL_CRYP_STATE_READY;
2823
2824 /* Process unlocked */
2825 __HAL_UNLOCK(hcryp);
2826 return HAL_ERROR;
2827 }
2828 }
2829 while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
2830
2831 /* Turn back to ALGOMODE of the configuration */
2832 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2833
2834#endif /* End AES or CRYP */
2835 }
2836
2837 else /*Algorithm CTR */
2838 {
2839 /* Set the Key*/
2840 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2841 }
2842
2843 /* Set IV */
2844 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2845 {
2846 /* Set the Initialization Vector*/
2847#if defined (AES)
2848 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2849 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2850 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2851 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2852#else /* CRYP */
2853 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2854 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2855 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2856 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2857#endif /* End AES or CRYP */
2858 }
2859 } /* if (DoKeyIVConfig == 1U) */
2860
2861 /* Set the phase */
2862 hcryp->Phase = CRYP_PHASE_PROCESS;
2863 if (hcryp->Size != 0U)
2864 {
2865
2866#if defined (AES)
2867
2868 /* Enable computation complete flag and error interrupts */
2869 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
2870
2871 /* Enable CRYP */
2872 __HAL_CRYP_ENABLE(hcryp);
2873
2874 /* Increment the pointer before writing the input block in the IN FIFO to make sure that
2875 when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
2876 and it is ready for the next operation. */
2877 hcryp->CrypInCount++;
2878 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2879 hcryp->CrypInCount++;
2880 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2881 hcryp->CrypInCount++;
2882 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2883 hcryp->CrypInCount++;
2884 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2885
2886#else /* CRYP */
2887
2888 /* Enable interrupts */
2889 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2890
2891 /* Enable CRYP */
2892 __HAL_CRYP_ENABLE(hcryp);
2893
2894#endif /* End AES or CRYP */
2895 }
2896 else
2897 {
2898 /* Process locked */
2899 __HAL_UNLOCK(hcryp);
2900
2901 /* Change the CRYP state */
2902 hcryp->State = HAL_CRYP_STATE_READY;
2903 }
2904
2905 /* Return function status */
2906 return HAL_OK;
2907}
2914static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
2915{
2916 __IO uint32_t count = 0U;
2917 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2918
2919 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2920 {
2921 if (hcryp->KeyIVConfig == 1U)
2922 {
2923 /* If the Key and IV configuration has to be done only once
2924 and if it has already been done, skip it */
2925 DoKeyIVConfig = 0U;
2926 }
2927 else
2928 {
2929 /* If the Key and IV configuration has to be done only once
2930 and if it has not been done already, do it and set KeyIVConfig
2931 to keep track it won't have to be done again next time */
2932 hcryp->KeyIVConfig = 1U;
2933 }
2934 }
2935 if (DoKeyIVConfig == 1U)
2936 {
2937 /* Key preparation for ECB/CBC */
2938 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2939 {
2940#if defined (AES)
2941 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
2942 {
2943 /* Set key preparation for decryption operating mode*/
2944 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2945
2946 /* Set the Key*/
2947 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2948
2949 /* Enable CRYP */
2950 __HAL_CRYP_ENABLE(hcryp);
2951
2952 /* Wait for CCF flag to be raised */
2953 count = CRYP_TIMEOUT_KEYPREPARATION;
2954 do
2955 {
2956 count-- ;
2957 if (count == 0U)
2958 {
2959 /* Disable the CRYP peripheral clock */
2960 __HAL_CRYP_DISABLE(hcryp);
2961
2962 /* Change state */
2963 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2964 hcryp->State = HAL_CRYP_STATE_READY;
2965
2966 /* Process unlocked */
2967 __HAL_UNLOCK(hcryp);
2968 return HAL_ERROR;
2969 }
2970 }
2971 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2972
2973 /* Clear CCF Flag */
2974 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2975
2976 /* Return to decryption operating mode(Mode 3)*/
2977 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2978 }
2979 else /*Mode 4 : decryption & key preparation*/
2980 {
2981 /* Set the Key*/
2982 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2983
2984 /* Set decryption & Key preparation operating mode*/
2985 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2986 }
2987#else /* CRYP */
2988 /* change ALGOMODE to key preparation for decryption*/
2989 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2990
2991 /* Set the Key*/
2992 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2993
2994 /* Enable CRYP */
2995 __HAL_CRYP_ENABLE(hcryp);
2996
2997 /* Wait for BUSY flag to be raised */
2998 count = CRYP_TIMEOUT_KEYPREPARATION;
2999 do
3000 {
3001 count-- ;
3002 if (count == 0U)
3003 {
3004 /* Disable the CRYP peripheral clock */
3005 __HAL_CRYP_DISABLE(hcryp);
3006
3007 /* Change state */
3008 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3009 hcryp->State = HAL_CRYP_STATE_READY;
3010
3011 /* Process unlocked */
3012 __HAL_UNLOCK(hcryp);
3013 return HAL_ERROR;
3014 }
3015 }
3016 while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
3017
3018 /* Turn back to ALGOMODE of the configuration */
3019 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
3020
3021#endif /* End AES or CRYP */
3022 }
3023 else /*Algorithm CTR */
3024 {
3025 /* Set the Key*/
3026 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3027 }
3028
3029 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
3030 {
3031 /* Set the Initialization Vector*/
3032#if defined (AES)
3033 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3034 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3035 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3036 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3037#else /* CRYP */
3038 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3039 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3040 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3041 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3042#endif /* End AES or CRYP */
3043 }
3044 } /* if (DoKeyIVConfig == 1U) */
3045
3046 /* Set the phase */
3047 hcryp->Phase = CRYP_PHASE_PROCESS;
3048
3049 if (hcryp->Size != 0U)
3050 {
3051 /* Set the input and output addresses and start DMA transfer */
3052 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
3053 }
3054 else
3055 {
3056 /* Process unlocked */
3057 __HAL_UNLOCK(hcryp);
3058
3059 /* Change the CRYP state */
3060 hcryp->State = HAL_CRYP_STATE_READY;
3061 }
3062
3063 /* Return function status */
3064 return HAL_OK;
3065}
3066
3067
3073static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
3074{
3075 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3076
3077 /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
3078 in the DMACR register */
3079#if defined (CRYP)
3080 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
3081
3082#else /* AES */
3083 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
3084
3085 /* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */
3086 if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
3087 {
3088 /* Clear CCF flag */
3089 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3090
3091 /* Change the CRYP state to ready */
3092 hcryp->State = HAL_CRYP_STATE_READY;
3093
3094 /* Process Unlocked */
3095 __HAL_UNLOCK(hcryp);
3096 }
3097#endif /* End AES or CRYP */
3098
3099 /* Call input data transfer complete callback */
3100#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3101 /*Call registered Input complete callback*/
3102 hcryp->InCpltCallback(hcryp);
3103#else
3104 /*Call legacy weak Input complete callback*/
3105 HAL_CRYP_InCpltCallback(hcryp);
3106#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3107}
3108
3114static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
3115{
3116 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3117
3118 /* Disable the DMA transfer for output FIFO request by resetting
3119 the DOEN bit in the DMACR register */
3120
3121#if defined (CRYP)
3122
3123 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
3124 #if defined (CRYP_CR_ALGOMODE_AES_GCM)
3125 if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
3126 {
3127 /* Disable CRYP (not allowed in GCM)*/
3128 __HAL_CRYP_DISABLE(hcryp);
3129 }
3130
3131 #else /*NO GCM CCM */
3132 /* Disable CRYP */
3133 __HAL_CRYP_DISABLE(hcryp);
3134 #endif /* GCM CCM defined*/
3135#else /* AES */
3136
3137 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
3138
3139 /* Clear CCF flag */
3140 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3141
3142 if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
3143 {
3144 /* Disable CRYP (not allowed in GCM)*/
3145 __HAL_CRYP_DISABLE(hcryp);
3146 }
3147#endif /* End AES or CRYP */
3148
3149 /* Change the CRYP state to ready */
3150 hcryp->State = HAL_CRYP_STATE_READY;
3151
3152 /* Process unlocked */
3153 __HAL_UNLOCK(hcryp);
3154 /* Call output data transfer complete callback */
3155#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3156 /*Call registered Output complete callback*/
3157 hcryp->OutCpltCallback(hcryp);
3158#else
3159 /*Call legacy weak Output complete callback*/
3160 HAL_CRYP_OutCpltCallback(hcryp);
3161#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3162}
3163
3169static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
3170{
3171 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3172
3173 /* Change the CRYP peripheral state */
3174 hcryp->State = HAL_CRYP_STATE_READY;
3175
3176 /* DMA error code field */
3177 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3178
3179#if defined (AES)
3180
3181 /* Clear CCF flag */
3182 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3183
3184#endif /* AES */
3185
3186 /* Call error callback */
3187#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3188 /*Call registered error callback*/
3189 hcryp->ErrorCallback(hcryp);
3190#else
3191 /*Call legacy weak error callback*/
3192 HAL_CRYP_ErrorCallback(hcryp);
3193#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3194}
3195
3205static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
3206{
3207 /* Set the CRYP DMA transfer complete callback */
3208 hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
3209
3210 /* Set the DMA input error callback */
3211 hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
3212
3213 /* Set the CRYP DMA transfer complete callback */
3214 hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
3215
3216 /* Set the DMA output error callback */
3217 hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
3218
3219#if defined (CRYP)
3220
3221 /* Enable CRYP */
3222 __HAL_CRYP_ENABLE(hcryp);
3223
3224 /* Enable the input DMA Stream */
3225 if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size) != HAL_OK)
3226 {
3227 /* DMA error code field */
3228 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3229
3230 /* Call error callback */
3231#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3232 /*Call registered error callback*/
3233 hcryp->ErrorCallback(hcryp);
3234#else
3235 /*Call legacy weak error callback*/
3236 HAL_CRYP_ErrorCallback(hcryp);
3237#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3238 }
3239 /* Enable the output DMA Stream */
3240 if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size) != HAL_OK)
3241 {
3242 /* DMA error code field */
3243 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3244
3245 /* Call error callback */
3246#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3247 /*Call registered error callback*/
3248 hcryp->ErrorCallback(hcryp);
3249#else
3250 /*Call legacy weak error callback*/
3251 HAL_CRYP_ErrorCallback(hcryp);
3252#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3253 }
3254 /* Enable In/Out DMA request */
3255 hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
3256
3257#else /* AES */
3258
3259 if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
3260 && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
3261 {
3262 /* Enable CRYP (not allowed in GCM & CCM)*/
3263 __HAL_CRYP_ENABLE(hcryp);
3264 }
3265
3266 /* Enable the DMA input stream */
3267 if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
3268 {
3269 /* DMA error code field */
3270 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3271
3272 /* Call error callback */
3273#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3274 /*Call registered error callback*/
3275 hcryp->ErrorCallback(hcryp);
3276#else
3277 /*Call legacy weak error callback*/
3278 HAL_CRYP_ErrorCallback(hcryp);
3279#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3280 }
3281 /* Enable the DMA output stream */
3282 if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK)
3283 {
3284 /* DMA error code field */
3285 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3286
3287 /* Call error callback */
3288#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3289 /*Call registered error callback*/
3290 hcryp->ErrorCallback(hcryp);
3291#else
3292 /*Call legacy weak error callback*/
3293 HAL_CRYP_ErrorCallback(hcryp);
3294#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3295 }
3296 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
3297 /* Enable In and Out DMA requests */
3298 if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
3299 {
3300 /* Enable only In DMA requests for CCM*/
3301 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN));
3302 }
3303 else
3304 {
3305 /* Enable In and Out DMA requests */
3306 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
3307 }
3308#endif /* End AES or CRYP */
3309}
3310
3318static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3319{
3320
3321 uint32_t temp[4]; /* Temporary CrypOutBuff */
3322 uint32_t i;
3323#if defined (CRYP)
3324 uint16_t incount; /* Temporary CrypInCount Value */
3325 uint16_t outcount; /* Temporary CrypOutCount Value */
3326#endif
3327
3328#if defined (CRYP)
3329
3330 /*Temporary CrypOutCount Value*/
3331 incount = hcryp->CrypInCount;
3332
3333 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3334 {
3335 /* Write the input block in the IN FIFO */
3336 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3337 hcryp->CrypInCount++;
3338 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3339 hcryp->CrypInCount++;
3340 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3341 hcryp->CrypInCount++;
3342 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3343 hcryp->CrypInCount++;
3344 }
3345
3346 /* Wait for OFNE flag to be raised */
3347 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
3348 {
3349 /* Disable the CRYP peripheral clock */
3350 __HAL_CRYP_DISABLE(hcryp);
3351
3352 /* Change state & error code*/
3353 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3354 hcryp->State = HAL_CRYP_STATE_READY;
3355
3356 /* Process unlocked */
3357 __HAL_UNLOCK(hcryp);
3358#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3359 /*Call registered error callback*/
3360 hcryp->ErrorCallback(hcryp);
3361#else
3362 /*Call legacy weak error callback*/
3363 HAL_CRYP_ErrorCallback(hcryp);
3364#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3365 }
3366
3367 /*Temporary CrypOutCount Value*/
3368 outcount = hcryp->CrypOutCount;
3369
3370 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3371 {
3372 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3373 for (i = 0U; i < 4U; i++)
3374 {
3375 temp[i] = hcryp->Instance->DOUT;
3376 }
3377 i = 0U;
3378 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3379 {
3380 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3381 hcryp->CrypOutCount++;
3382 i++;
3383 }
3384 }
3385
3386#else /* AES */
3387
3388 /* Write the input block in the IN FIFO */
3389 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3390 hcryp->CrypInCount++;
3391 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3392 hcryp->CrypInCount++;
3393 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3394 hcryp->CrypInCount++;
3395 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3396 hcryp->CrypInCount++;
3397
3398 /* Wait for CCF flag to be raised */
3399 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3400 {
3401 /* Disable the CRYP peripheral clock */
3402 __HAL_CRYP_DISABLE(hcryp);
3403
3404 /* Change state */
3405 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3406 hcryp->State = HAL_CRYP_STATE_READY;
3407
3408 /* Process unlocked */
3409 __HAL_UNLOCK(hcryp);
3410#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3411 /*Call registered error callback*/
3412 hcryp->ErrorCallback(hcryp);
3413#else
3414 /*Call legacy weak error callback*/
3415 HAL_CRYP_ErrorCallback(hcryp);
3416#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3417 }
3418
3419 /* Clear CCF Flag */
3420 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3421
3422 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
3423 for (i = 0U; i < 4U; i++)
3424 {
3425 temp[i] = hcryp->Instance->DOUTR;
3426 }
3427 i = 0U;
3428 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3429 {
3430 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3431 hcryp->CrypOutCount++;
3432 i++;
3433 }
3434#endif /* End AES or CRYP */
3435}
3436
3445static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
3446{
3447 uint32_t temp[4]; /* Temporary CrypOutBuff */
3448 uint32_t i;
3449#if defined (CRYP)
3450 uint16_t incount; /* Temporary CrypInCount Value */
3451 uint16_t outcount; /* Temporary CrypOutCount Value */
3452#endif
3453
3454 if (hcryp->State == HAL_CRYP_STATE_BUSY)
3455 {
3456#if defined (CRYP)
3457
3458 /*Temporary CrypOutCount Value*/
3459 incount = hcryp->CrypInCount;
3460 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3461 {
3462 /* Write the input block in the IN FIFO */
3463 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3464 hcryp->CrypInCount++;
3465 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3466 hcryp->CrypInCount++;
3467 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3468 hcryp->CrypInCount++;
3469 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3470 hcryp->CrypInCount++;
3471 if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
3472 {
3473 /* Disable interrupts */
3474 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3475
3476 /* Call the input data transfer complete callback */
3477#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3478 /*Call registered Input complete callback*/
3479 hcryp->InCpltCallback(hcryp);
3480#else
3481 /*Call legacy weak Input complete callback*/
3482 HAL_CRYP_InCpltCallback(hcryp);
3483#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3484 }
3485 }
3486 /*Temporary CrypOutCount Value*/
3487 outcount = hcryp->CrypOutCount;
3488
3489 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3490 {
3491 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3492 for (i = 0U; i < 4U; i++)
3493 {
3494 temp[i] = hcryp->Instance->DOUT;
3495 }
3496 i = 0U;
3497 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3498 {
3499 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3500 hcryp->CrypOutCount++;
3501 i++;
3502 }
3503 if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
3504 {
3505 /* Disable interrupts */
3506 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3507
3508 /* Change the CRYP state */
3509 hcryp->State = HAL_CRYP_STATE_READY;
3510
3511 /* Disable CRYP */
3512 __HAL_CRYP_DISABLE(hcryp);
3513
3514 /* Process unlocked */
3515 __HAL_UNLOCK(hcryp);
3516
3517 /* Call Output transfer complete callback */
3518#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3519 /*Call registered Output complete callback*/
3520 hcryp->OutCpltCallback(hcryp);
3521#else
3522 /*Call legacy weak Output complete callback*/
3523 HAL_CRYP_OutCpltCallback(hcryp);
3524#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3525 }
3526 }
3527
3528#else /*AES*/
3529
3530 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
3531 for (i = 0U; i < 4U; i++)
3532 {
3533 temp[i] = hcryp->Instance->DOUTR;
3534 }
3535 i = 0U;
3536 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3537 {
3538 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3539 hcryp->CrypOutCount++;
3540 i++;
3541 }
3542
3543 if (hcryp->CrypOutCount == (hcryp->Size / 4U))
3544 {
3545 /* Disable Computation Complete flag and errors interrupts */
3546 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
3547
3548 /* Change the CRYP state */
3549 hcryp->State = HAL_CRYP_STATE_READY;
3550
3551 /* Disable CRYP */
3552 __HAL_CRYP_DISABLE(hcryp);
3553
3554 /* Process Unlocked */
3555 __HAL_UNLOCK(hcryp);
3556
3557 /* Call Output transfer complete callback */
3558#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3559 /*Call registered Output complete callback*/
3560 hcryp->OutCpltCallback(hcryp);
3561#else
3562 /*Call legacy weak Output complete callback*/
3563 HAL_CRYP_OutCpltCallback(hcryp);
3564#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3565 }
3566 else
3567 {
3568 /* Write the input block in the IN FIFO */
3569 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3570 hcryp->CrypInCount++;
3571 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3572 hcryp->CrypInCount++;
3573 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3574 hcryp->CrypInCount++;
3575 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3576 hcryp->CrypInCount++;
3577
3578 if (hcryp->CrypInCount == (hcryp->Size / 4U))
3579 {
3580 /* Call Input transfer complete callback */
3581#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3582 /*Call registered Input complete callback*/
3583 hcryp->InCpltCallback(hcryp);
3584#else
3585 /*Call legacy weak Input complete callback*/
3586 HAL_CRYP_InCpltCallback(hcryp);
3587#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3588 }
3589 }
3590#endif /* End AES or CRYP */
3591
3592 }
3593 else
3594 {
3595 /* Busy error code field */
3596 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
3597#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3598 /*Call registered error callback*/
3599 hcryp->ErrorCallback(hcryp);
3600#else
3601 /*Call legacy weak error callback*/
3602 HAL_CRYP_ErrorCallback(hcryp);
3603#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3604 }
3605}
3606
3614static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
3615{
3616#if defined (CRYP)
3617
3618 switch (KeySize)
3619 {
3620 case CRYP_KEYSIZE_256B:
3621 hcryp->Instance->K0LR = *(uint32_t *)(hcryp->Init.pKey);
3622 hcryp->Instance->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3623 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3624 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3625 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4);
3626 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5);
3627 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6);
3628 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7);
3629 break;
3630 case CRYP_KEYSIZE_192B:
3631 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
3632 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3633 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3634 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3635 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
3636 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
3637 break;
3638 case CRYP_KEYSIZE_128B:
3639 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey);
3640 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3641 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3642 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3643
3644 break;
3645 default:
3646 break;
3647 }
3648#else /*AES*/
3649 switch (KeySize)
3650 {
3651 case CRYP_KEYSIZE_256B:
3652 hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
3653 hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1);
3654 hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2);
3655 hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3);
3656 hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4);
3657 hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5);
3658 hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6);
3659 hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7);
3660 break;
3661 case CRYP_KEYSIZE_128B:
3662 hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
3663 hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1);
3664 hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2);
3665 hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3);
3666
3667 break;
3668 default:
3669 break;
3670 }
3671#endif /* End AES or CRYP */
3672}
3673
3674#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
3682static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3683{
3684 uint32_t tickstart;
3685 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
3686 uint16_t outcount; /* Temporary CrypOutCount Value */
3687 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3688
3689 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3690 {
3691 if (hcryp->KeyIVConfig == 1U)
3692 {
3693 /* If the Key and IV configuration has to be done only once
3694 and if it has already been done, skip it */
3695 DoKeyIVConfig = 0U;
3696 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3697 }
3698 else
3699 {
3700 /* If the Key and IV configuration has to be done only once
3701 and if it has not been done already, do it and set KeyIVConfig
3702 to keep track it won't have to be done again next time */
3703 hcryp->KeyIVConfig = 1U;
3704 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3705 }
3706 }
3707 else
3708 {
3709 hcryp->SizesSum = hcryp->Size;
3710 }
3711
3712 if (DoKeyIVConfig == 1U)
3713 {
3714 /* Reset CrypHeaderCount */
3715 hcryp->CrypHeaderCount = 0U;
3716
3717 /****************************** Init phase **********************************/
3718
3719 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3720
3721 /* Set the key */
3722 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3723
3724#if defined(CRYP)
3725
3726 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3727 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3728 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3729 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3730 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3731
3732 /* Enable the CRYP peripheral */
3733 __HAL_CRYP_ENABLE(hcryp);
3734
3735 /* Get tick */
3736 tickstart = HAL_GetTick();
3737
3738 /*Wait for the CRYPEN bit to be cleared*/
3739 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
3740 {
3741 /* Check for the Timeout */
3742 if (Timeout != HAL_MAX_DELAY)
3743 {
3744 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3745 {
3746 /* Disable the CRYP peripheral clock */
3747 __HAL_CRYP_DISABLE(hcryp);
3748
3749 /* Change state */
3750 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3751 hcryp->State = HAL_CRYP_STATE_READY;
3752
3753 /* Process unlocked */
3754 __HAL_UNLOCK(hcryp);
3755 return HAL_ERROR;
3756 }
3757 }
3758 }
3759
3760#else /* AES */
3761 /* Workaround 1 : only AES.
3762 Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
3763 enabling the IP, datatype different from 32 bits can be configured.*/
3764 /* Select DATATYPE 32 */
3765 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3766
3767 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3768 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3769 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3770 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3771 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3772
3773 /* Enable the CRYP peripheral */
3774 __HAL_CRYP_ENABLE(hcryp);
3775
3776 /* just wait for hash computation */
3777 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3778 {
3779 /* Change state */
3780 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3781 hcryp->State = HAL_CRYP_STATE_READY;
3782
3783 /* Process unlocked & return error */
3784 __HAL_UNLOCK(hcryp);
3785 return HAL_ERROR;
3786 }
3787 /* Clear CCF flag */
3788 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3789
3790#endif /* End AES or CRYP */
3791
3792 /************************ Header phase *************************************/
3793
3794 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
3795 {
3796 return HAL_ERROR;
3797 }
3798
3799 /*************************Payload phase ************************************/
3800
3801 /* Set the phase */
3802 hcryp->Phase = CRYP_PHASE_PROCESS;
3803
3804#if defined(CRYP)
3805
3806 /* Disable the CRYP peripheral */
3807 __HAL_CRYP_DISABLE(hcryp);
3808
3809 /* Select payload phase once the header phase is performed */
3810 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3811
3812 /* Enable the CRYP peripheral */
3813 __HAL_CRYP_ENABLE(hcryp);
3814
3815#else /* AES */
3816
3817 /* Select payload phase once the header phase is performed */
3818 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3819
3820#endif /* End AES or CRYP */
3821 } /* if (DoKeyIVConfig == 1U) */
3822
3823 if ((hcryp->Size % 16U) != 0U)
3824 {
3825 /* recalculate wordsize */
3826 wordsize = ((wordsize / 4U) * 4U) ;
3827 }
3828
3829 /* Get tick */
3830 tickstart = HAL_GetTick();
3831 /*Temporary CrypOutCount Value*/
3832 outcount = hcryp->CrypOutCount;
3833
3834 /* Write input data and get output Data */
3835 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
3836 {
3837 /* Write plain data and get cipher data */
3838 CRYP_AES_ProcessData(hcryp, Timeout);
3839
3840 /*Temporary CrypOutCount Value*/
3841 outcount = hcryp->CrypOutCount;
3842
3843 /* Check for the Timeout */
3844 if (Timeout != HAL_MAX_DELAY)
3845 {
3846 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3847 {
3848 /* Disable the CRYP peripheral clock */
3849 __HAL_CRYP_DISABLE(hcryp);
3850
3851 /* Change state & error code */
3852 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3853 hcryp->State = HAL_CRYP_STATE_READY;
3854
3855 /* Process unlocked */
3856 __HAL_UNLOCK(hcryp);
3857 return HAL_ERROR;
3858 }
3859 }
3860 }
3861
3862 if ((hcryp->Size % 16U) != 0U)
3863 {
3864 /* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of
3865 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption
3866 is selected, then the TAG message will be wrong.*/
3867 CRYP_Workaround(hcryp, Timeout);
3868 }
3869
3870 /* Return function status */
3871 return HAL_OK;
3872}
3873
3880static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
3881{
3882 __IO uint32_t count = 0U;
3883 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3884#if defined(AES)
3885 uint32_t loopcounter;
3886 uint32_t lastwordsize;
3887 uint32_t npblb;
3888#endif /* AES */
3889
3890 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3891 {
3892 if (hcryp->KeyIVConfig == 1U)
3893 {
3894 /* If the Key and IV configuration has to be done only once
3895 and if it has already been done, skip it */
3896 DoKeyIVConfig = 0U;
3897 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3898 }
3899 else
3900 {
3901 /* If the Key and IV configuration has to be done only once
3902 and if it has not been done already, do it and set KeyIVConfig
3903 to keep track it won't have to be done again next time */
3904 hcryp->KeyIVConfig = 1U;
3905 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3906 }
3907 }
3908 else
3909 {
3910 hcryp->SizesSum = hcryp->Size;
3911 }
3912
3913 /* Configure Key, IV and process message (header and payload) */
3914 if (DoKeyIVConfig == 1U)
3915 {
3916 /* Reset CrypHeaderCount */
3917 hcryp->CrypHeaderCount = 0U;
3918
3919 /******************************* Init phase *********************************/
3920
3921 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3922
3923 /* Set the key */
3924 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3925
3926#if defined(CRYP)
3927 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3928 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3929 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3930 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3931 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3932
3933 /* Enable the CRYP peripheral */
3934 __HAL_CRYP_ENABLE(hcryp);
3935
3936 /*Wait for the CRYPEN bit to be cleared*/
3937 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3938 do
3939 {
3940 count-- ;
3941 if (count == 0U)
3942 {
3943 /* Disable the CRYP peripheral clock */
3944 __HAL_CRYP_DISABLE(hcryp);
3945
3946 /* Change state */
3947 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3948 hcryp->State = HAL_CRYP_STATE_READY;
3949
3950 /* Process unlocked */
3951 __HAL_UNLOCK(hcryp);
3952 return HAL_ERROR;
3953 }
3954 }
3955 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
3956
3957#else /* AES */
3958
3959 /* Workaround 1 : only AES
3960 Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re
3961 enabling the IP, datatype different from 32 bits can be configured.*/
3962 /* Select DATATYPE 32 */
3963 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3964
3965 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3966 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3967 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3968 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3969 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3970
3971 /* Enable the CRYP peripheral */
3972 __HAL_CRYP_ENABLE(hcryp);
3973
3974 /* just wait for hash computation */
3975 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3976 do
3977 {
3978 count-- ;
3979 if (count == 0U)
3980 {
3981 /* Disable the CRYP peripheral clock */
3982 __HAL_CRYP_DISABLE(hcryp);
3983
3984 /* Change state */
3985 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3986 hcryp->State = HAL_CRYP_STATE_READY;
3987
3988 /* Process unlocked */
3989 __HAL_UNLOCK(hcryp);
3990 return HAL_ERROR;
3991 }
3992 }
3993 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
3994
3995 /* Clear CCF flag */
3996 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3997
3998#endif /* End AES or CRYP */
3999
4000 /***************************** Header phase *********************************/
4001
4002#if defined(CRYP)
4003
4004 /* Select header phase */
4005 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4006
4007 /* Enable interrupts */
4008 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
4009
4010 /* Enable CRYP */
4011 __HAL_CRYP_ENABLE(hcryp);
4012
4013#else /* AES */
4014
4015 /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/
4016 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
4017
4018 /* Select header phase */
4019 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4020
4021 /* Enable computation complete flag and error interrupts */
4022 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4023
4024 /* Enable the CRYP peripheral */
4025 __HAL_CRYP_ENABLE(hcryp);
4026
4027 if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
4028 {
4029 /* Set the phase */
4030 hcryp->Phase = CRYP_PHASE_PROCESS;
4031
4032 /* Select payload phase once the header phase is performed */
4033 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
4034
4035 /* Write the payload Input block in the IN FIFO */
4036 if (hcryp->Size == 0U)
4037 {
4038 /* Disable interrupts */
4039 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4040
4041 /* Change the CRYP state */
4042 hcryp->State = HAL_CRYP_STATE_READY;
4043
4044 /* Process unlocked */
4045 __HAL_UNLOCK(hcryp);
4046 }
4047 else if (hcryp->Size >= 16U)
4048 {
4049 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4050 hcryp->CrypInCount++;
4051 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4052 hcryp->CrypInCount++;
4053 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4054 hcryp->CrypInCount++;
4055 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4056 hcryp->CrypInCount++;
4057 if (hcryp->CrypInCount == (hcryp->Size / 4U))
4058 {
4059 /* Call Input transfer complete callback */
4060#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4061 /*Call registered Input complete callback*/
4062 hcryp->InCpltCallback(hcryp);
4063#else
4064 /*Call legacy weak Input complete callback*/
4065 HAL_CRYP_InCpltCallback(hcryp);
4066#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4067 }
4068 }
4069 else /* Size < 16Bytes : first block is the last block*/
4070 {
4071 /* Workaround not implemented*/
4072 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4073 Workaround is implemented in polling mode, so if last block of
4074 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
4075
4076 /* Compute the number of padding bytes in last block of payload */
4077 npblb = 16U - (uint32_t)(hcryp->Size);
4078
4079 /* Number of valid words (lastwordsize) in last block */
4080 if ((npblb % 4U) == 0U)
4081 {
4082 lastwordsize = (16U - npblb) / 4U;
4083 }
4084 else
4085 {
4086 lastwordsize = ((16U - npblb) / 4U) + 1U;
4087 }
4088
4089 /* last block optionally pad the data with zeros*/
4090 for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
4091 {
4092 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4093 hcryp->CrypInCount++;
4094 }
4095 while (loopcounter < 4U)
4096 {
4097 /* pad the data with zeros to have a complete block */
4098 hcryp->Instance->DINR = 0x0U;
4099 loopcounter++;
4100 }
4101 }
4102 }
4103 else if ((hcryp->Init.HeaderSize) < 4U)
4104 {
4105 for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
4106 {
4107 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4108 hcryp->CrypHeaderCount++ ;
4109 }
4110 while (loopcounter < 4U)
4111 {
4112 /* pad the data with zeros to have a complete block */
4113 hcryp->Instance->DINR = 0x0U;
4114 loopcounter++;
4115 }
4116 /* Set the phase */
4117 hcryp->Phase = CRYP_PHASE_PROCESS;
4118
4119 /* Select payload phase once the header phase is performed */
4120 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4121
4122 /* Call Input transfer complete callback */
4123#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4124 /*Call registered Input complete callback*/
4125 hcryp->InCpltCallback(hcryp);
4126#else
4127 /*Call legacy weak Input complete callback*/
4128 HAL_CRYP_InCpltCallback(hcryp);
4129#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4130 }
4131 else if ((hcryp->Init.HeaderSize) >= 4U)
4132 {
4133 /* Write the input block in the IN FIFO */
4134 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4135 hcryp->CrypHeaderCount++;
4136 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4137 hcryp->CrypHeaderCount++;
4138 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4139 hcryp->CrypHeaderCount++;
4140 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4141 hcryp->CrypHeaderCount++;
4142 }
4143 else
4144 {
4145 /* Nothing to do */
4146 }
4147
4148#endif /* End AES or CRYP */
4149 } /* end of if (DoKeyIVConfig == 1U) */
4150
4151 /* Return function status */
4152 return HAL_OK;
4153}
4154
4155
4162static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4163{
4164 __IO uint32_t count = 0U;
4165 uint32_t wordsize;
4166 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4167
4168 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4169 {
4170 if (hcryp->KeyIVConfig == 1U)
4171 {
4172 /* If the Key and IV configuration has to be done only once
4173 and if it has already been done, skip it */
4174 DoKeyIVConfig = 0U;
4175 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4176 }
4177 else
4178 {
4179 /* If the Key and IV configuration has to be done only once
4180 and if it has not been done already, do it and set KeyIVConfig
4181 to keep track it won't have to be done again next time */
4182 hcryp->KeyIVConfig = 1U;
4183 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4184 }
4185 }
4186 else
4187 {
4188 hcryp->SizesSum = hcryp->Size;
4189 }
4190
4191 if (DoKeyIVConfig == 1U)
4192 {
4193 /* Reset CrypHeaderCount */
4194 hcryp->CrypHeaderCount = 0U;
4195
4196 /*************************** Init phase ************************************/
4197
4198 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4199
4200 /* Set the key */
4201 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4202
4203#if defined(CRYP)
4204 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4205 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
4206 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4207 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4208 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4209
4210 /* Enable the CRYP peripheral */
4211 __HAL_CRYP_ENABLE(hcryp);
4212
4213 /*Wait for the CRYPEN bit to be cleared*/
4214 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4215 do
4216 {
4217 count-- ;
4218 if (count == 0U)
4219 {
4220 /* Disable the CRYP peripheral clock */
4221 __HAL_CRYP_DISABLE(hcryp);
4222
4223 /* Change state */
4224 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4225 hcryp->State = HAL_CRYP_STATE_READY;
4226
4227 /* Process unlocked */
4228 __HAL_UNLOCK(hcryp);
4229 return HAL_ERROR;
4230 }
4231 }
4232 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4233
4234#else /* AES */
4235
4236 /*Workaround 1 : only AES
4237 Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
4238 enabling the IP, datatype different from 32 bits can be configured.*/
4239 /* Select DATATYPE 32 */
4240 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
4241
4242 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4243 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
4244 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4245 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4246 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4247
4248 /* Enable the CRYP peripheral */
4249 __HAL_CRYP_ENABLE(hcryp);
4250
4251 /* just wait for hash computation */
4252 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4253 do
4254 {
4255 count-- ;
4256 if (count == 0U)
4257 {
4258 /* Disable the CRYP peripheral clock */
4259 __HAL_CRYP_DISABLE(hcryp);
4260
4261 /* Change state */
4262 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4263 hcryp->State = HAL_CRYP_STATE_READY;
4264
4265 /* Process unlocked */
4266 __HAL_UNLOCK(hcryp);
4267 return HAL_ERROR;
4268 }
4269 }
4270 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
4271
4272 /* Clear CCF flag */
4273 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4274
4275#endif /* End AES or CRYP */
4276
4277 /************************ Header phase *************************************/
4278
4279 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
4280 {
4281 return HAL_ERROR;
4282 }
4283
4284 /************************ Payload phase ************************************/
4285
4286 /* Set the phase */
4287 hcryp->Phase = CRYP_PHASE_PROCESS;
4288
4289#if defined(CRYP)
4290
4291 /* Disable the CRYP peripheral */
4292 __HAL_CRYP_DISABLE(hcryp);
4293
4294#endif /* CRYP */
4295
4296 /* Select payload phase once the header phase is performed */
4297 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4298
4299 } /* if (DoKeyIVConfig == 1U) */
4300
4301 if (hcryp->Size != 0U)
4302 {
4303 /* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4304 Workaround is implemented in polling mode, so if last block of
4305 payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
4306 /* Set the input and output addresses and start DMA transfer */
4307 if ((hcryp->Size % 16U) == 0U)
4308 {
4309 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
4310 }
4311 else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
4312 {
4313 wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
4314
4315 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
4316 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
4317 (uint32_t)(hcryp->pCrypOutBuffPtr));
4318 }
4319 }
4320 else
4321 {
4322 /* Process unLocked */
4323 __HAL_UNLOCK(hcryp);
4324
4325 /* Change the CRYP state and phase */
4326 hcryp->State = HAL_CRYP_STATE_READY;
4327 }
4328
4329 /* Return function status */
4330 return HAL_OK;
4331}
4332
4333
4342static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4343{
4344 uint32_t tickstart;
4345 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
4346 uint16_t outcount; /* Temporary CrypOutCount Value */
4347 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4348#if defined(AES)
4349 uint32_t loopcounter;
4350 uint32_t npblb;
4351 uint32_t lastwordsize;
4352#endif /* AES */
4353
4354 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4355 {
4356 if (hcryp->KeyIVConfig == 1U)
4357 {
4358 /* If the Key and IV configuration has to be done only once
4359 and if it has already been done, skip it */
4360 DoKeyIVConfig = 0U;
4361 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4362 }
4363 else
4364 {
4365 /* If the Key and IV configuration has to be done only once
4366 and if it has not been done already, do it and set KeyIVConfig
4367 to keep track it won't have to be done again next time */
4368 hcryp->KeyIVConfig = 1U;
4369 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4370 }
4371 }
4372 else
4373 {
4374 hcryp->SizesSum = hcryp->Size;
4375 }
4376
4377 if (DoKeyIVConfig == 1U)
4378 {
4379
4380 /* Reset CrypHeaderCount */
4381 hcryp->CrypHeaderCount = 0U;
4382
4383#if defined(CRYP)
4384
4385 /********************** Init phase ******************************************/
4386
4387 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4388
4389 /* Set the key */
4390 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4391
4392 /* Set the initialization vector (IV) with CTR1 information */
4393 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4394 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4395 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4396 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4397
4398
4399 /* Enable the CRYP peripheral */
4400 __HAL_CRYP_ENABLE(hcryp);
4401
4402 /*Write B0 packet into CRYP_DIN Register*/
4403 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4404 {
4405 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4406 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4407 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4408 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4409 }
4410 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4411 {
4412 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4413 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4414 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4415 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4416 }
4417 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4418 {
4419 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
4420 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
4421 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
4422 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
4423 }
4424 else
4425 {
4426 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
4427 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
4428 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
4429 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
4430 }
4431 /* Get tick */
4432 tickstart = HAL_GetTick();
4433
4434 /*Wait for the CRYPEN bit to be cleared*/
4435 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
4436 {
4437 /* Check for the Timeout */
4438 if (Timeout != HAL_MAX_DELAY)
4439 {
4440 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4441 {
4442 /* Disable the CRYP peripheral clock */
4443 __HAL_CRYP_DISABLE(hcryp);
4444
4445 /* Change state */
4446 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4447 hcryp->State = HAL_CRYP_STATE_READY;
4448
4449 /* Process unlocked */
4450 __HAL_UNLOCK(hcryp);
4451 return HAL_ERROR;
4452 }
4453 }
4454 }
4455#else /* AES */
4456 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
4457 /* Select header phase */
4458 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4459
4460 /* configured encryption mode */
4461 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4462
4463 /* Set the key */
4464 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4465
4466 /* Set the initialization vector with zero values*/
4467 hcryp->Instance->IVR3 = 0U;
4468 hcryp->Instance->IVR2 = 0U;
4469 hcryp->Instance->IVR1 = 0U;
4470 hcryp->Instance->IVR0 = 0U;
4471
4472 /* Enable the CRYP peripheral */
4473 __HAL_CRYP_ENABLE(hcryp);
4474
4475 /*Write the B0 packet into CRYP_DIN*/
4476 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
4477 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
4478 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
4479 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
4480
4481 /* wait until the end of computation */
4482 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4483 {
4484 /* Change state */
4485 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4486 hcryp->State = HAL_CRYP_STATE_READY;
4487
4488 /* Process unlocked & return error */
4489 __HAL_UNLOCK(hcryp);
4490 return HAL_ERROR;
4491 }
4492 /* Clear CCF flag */
4493 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4494
4495 /* Set the phase */
4496 hcryp->Phase = CRYP_PHASE_PROCESS;
4497
4498 /* From that point the whole message must be processed, first the Header then the payload.
4499 First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
4500
4501 if (hcryp->Init.HeaderSize != 0U)
4502 {
4503 if ((hcryp->Init.HeaderSize % 4U) == 0U)
4504 {
4505 /* HeaderSize %4, no padding */
4506 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
4507 {
4508 /* Write the Input block in the Data Input register */
4509 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4510 hcryp->CrypHeaderCount++ ;
4511 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4512 hcryp->CrypHeaderCount++ ;
4513 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4514 hcryp->CrypHeaderCount++ ;
4515 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4516 hcryp->CrypHeaderCount++ ;
4517
4518 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4519 {
4520 /* Disable the CRYP peripheral clock */
4521 __HAL_CRYP_DISABLE(hcryp);
4522
4523 /* Change state */
4524 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4525 hcryp->State = HAL_CRYP_STATE_READY;
4526
4527 /* Process unlocked */
4528 __HAL_UNLOCK(hcryp);
4529 return HAL_ERROR;
4530 }
4531 /* Clear CCF Flag */
4532 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4533 }
4534 }
4535 else
4536 {
4537 /*Write Header block in the IN FIFO without last block */
4538 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
4539 {
4540 /* Write the input block in the data input register */
4541 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4542 hcryp->CrypHeaderCount++ ;
4543 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4544 hcryp->CrypHeaderCount++ ;
4545 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4546 hcryp->CrypHeaderCount++ ;
4547 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4548 hcryp->CrypHeaderCount++ ;
4549
4550 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4551 {
4552 /* Disable the CRYP peripheral clock */
4553 __HAL_CRYP_DISABLE(hcryp);
4554
4555 /* Change state */
4556 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4557 hcryp->State = HAL_CRYP_STATE_READY;
4558
4559 /* Process unlocked */
4560 __HAL_UNLOCK(hcryp);
4561 return HAL_ERROR;
4562 }
4563 /* Clear CCF Flag */
4564 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4565 }
4566 /* Last block optionally pad the data with zeros*/
4567 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
4568 {
4569 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4570 hcryp->CrypHeaderCount++ ;
4571 }
4572 while (loopcounter < 4U)
4573 {
4574 /* Pad the data with zeros to have a complete block */
4575 hcryp->Instance->DINR = 0x0U;
4576 loopcounter++;
4577 }
4578
4579 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4580 {
4581 /* Disable the CRYP peripheral clock */
4582 __HAL_CRYP_DISABLE(hcryp);
4583
4584 /* Change state */
4585 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4586 hcryp->State = HAL_CRYP_STATE_READY;
4587
4588 /* Process unlocked */
4589 __HAL_UNLOCK(hcryp);
4590 return HAL_ERROR;
4591 }
4592 /* Clear CCF flag */
4593 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4594 }
4595 }
4596 } /* if (DoKeyIVConfig == 1U) */
4597 /* Then the payload: cleartext payload (not the ciphertext payload).
4598 Write input Data, no output Data to get */
4599 if (hcryp->Size != 0U)
4600 {
4601 if ((hcryp->Size % 16U) != 0U)
4602 {
4603 /* recalculate wordsize */
4604 wordsize = ((wordsize / 4U) * 4U) ;
4605 }
4606
4607 /* Get tick */
4608 tickstart = HAL_GetTick();
4609 /*Temporary CrypOutCount Value*/
4610 outcount = hcryp->CrypOutCount;
4611
4612 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4613 {
4614 /* Write plain data and get cipher data */
4615 CRYP_AES_ProcessData(hcryp, Timeout);
4616
4617 /*Temporary CrypOutCount Value*/
4618 outcount = hcryp->CrypOutCount;
4619
4620 /* Check for the Timeout */
4621 if (Timeout != HAL_MAX_DELAY)
4622 {
4623 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4624 {
4625 /* Disable the CRYP peripheral clock */
4626 __HAL_CRYP_DISABLE(hcryp);
4627
4628 /* Change state */
4629 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4630 hcryp->State = HAL_CRYP_STATE_READY;
4631
4632 /* Process unlocked */
4633 __HAL_UNLOCK(hcryp);
4634 return HAL_ERROR;
4635 }
4636 }
4637 }
4638
4639 if ((hcryp->Size % 16U) != 0U)
4640 {
4641 /* Compute the number of padding bytes in last block of payload */
4642 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
4643
4644 /* Number of valid words (lastwordsize) in last block */
4645 if ((npblb % 4U) == 0U)
4646 {
4647 lastwordsize = (16U - npblb) / 4U;
4648 }
4649 else
4650 {
4651 lastwordsize = ((16U - npblb) / 4U) + 1U;
4652 }
4653 /* Last block optionally pad the data with zeros*/
4654 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
4655 {
4656 /* Write the last input block in the IN FIFO */
4657 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4658 hcryp->CrypInCount++;
4659 }
4660 while (loopcounter < 4U)
4661 {
4662 /* Pad the data with zeros to have a complete block */
4663 hcryp->Instance->DINR = 0U;
4664 loopcounter++;
4665 }
4666 /* Wait for CCF flag to be raised */
4667 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4668 {
4669 /* Disable the CRYP peripheral clock */
4670 __HAL_CRYP_DISABLE(hcryp);
4671
4672 /* Change state */
4673 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4674 hcryp->State = HAL_CRYP_STATE_READY;
4675
4676 /* Process unlocked */
4677 __HAL_UNLOCK(hcryp);
4678 return HAL_ERROR;
4679 }
4680 /* Clear CCF flag */
4681 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4682
4683 }
4684 }
4685#endif /* End AES or CRYP */
4686
4687#if defined(CRYP)
4688
4689 /************************* Header phase *************************************/
4690 /* Header block(B1) : associated data length expressed in bytes concatenated
4691 with Associated Data (A)*/
4692
4693 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
4694 {
4695 return HAL_ERROR;
4696 }
4697
4698 /********************** Payload phase ***************************************/
4699
4700 /* Set the phase */
4701 hcryp->Phase = CRYP_PHASE_PROCESS;
4702
4703 /* Disable the CRYP peripheral */
4704 __HAL_CRYP_DISABLE(hcryp);
4705
4706 /* Select payload phase once the header phase is performed */
4707 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4708
4709 /* Enable the CRYP peripheral */
4710 __HAL_CRYP_ENABLE(hcryp);
4711
4712 } /* if (DoKeyIVConfig == 1U) */
4713
4714 if ((hcryp->Size % 16U) != 0U)
4715 {
4716 /* recalculate wordsize */
4717 wordsize = ((wordsize / 4U) * 4U) ;
4718 }
4719 /* Get tick */
4720 tickstart = HAL_GetTick();
4721 /*Temporary CrypOutCount Value*/
4722 outcount = hcryp->CrypOutCount;
4723
4724 /* Write input data and get output data */
4725 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4726 {
4727 /* Write plain data and get cipher data */
4728 CRYP_AES_ProcessData(hcryp, Timeout);
4729
4730 /* Check for the Timeout */
4731 if (Timeout != HAL_MAX_DELAY)
4732 {
4733 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4734 {
4735 /* Disable the CRYP peripheral clock */
4736 __HAL_CRYP_DISABLE(hcryp);
4737
4738 /* Change state */
4739 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4740 hcryp->State = HAL_CRYP_STATE_READY;
4741
4742 /* Process unlocked */
4743 __HAL_UNLOCK(hcryp);
4744 return HAL_ERROR;
4745 }
4746 }
4747 }
4748
4749 if ((hcryp->Size % 16U) != 0U)
4750 {
4751 /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
4752 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
4753 is selected, then the TAG message will be wrong.*/
4754 CRYP_Workaround(hcryp, Timeout);
4755 }
4756#endif /* CRYP */
4757
4758 /* Return function status */
4759 return HAL_OK;
4760}
4761
4769static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
4770{
4771 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4772#if defined(CRYP)
4773 __IO uint32_t count = 0U;
4774#endif /* CRYP */
4775
4776 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4777 {
4778 if (hcryp->KeyIVConfig == 1U)
4779 {
4780 /* If the Key and IV configuration has to be done only once
4781 and if it has already been done, skip it */
4782 DoKeyIVConfig = 0U;
4783 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4784 }
4785 else
4786 {
4787 /* If the Key and IV configuration has to be done only once
4788 and if it has not been done already, do it and set KeyIVConfig
4789 to keep track it won't have to be done again next time */
4790 hcryp->KeyIVConfig = 1U;
4791 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4792 }
4793 }
4794 else
4795 {
4796 hcryp->SizesSum = hcryp->Size;
4797 }
4798
4799 /* Configure Key, IV and process message (header and payload) */
4800 if (DoKeyIVConfig == 1U)
4801 {
4802 /* Reset CrypHeaderCount */
4803 hcryp->CrypHeaderCount = 0U;
4804
4805#if defined(CRYP)
4806
4807 /************ Init phase ************/
4808
4809 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4810
4811 /* Set the key */
4812 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4813
4814 /* Set the initialization vector (IV) with CTR1 information */
4815 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4816 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4817 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4818 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4819
4820 /* Enable the CRYP peripheral */
4821 __HAL_CRYP_ENABLE(hcryp);
4822
4823 /*Write the B0 packet into CRYP_DIN Register*/
4824 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4825 {
4826 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4827 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4828 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4829 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4830 }
4831 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4832 {
4833 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4834 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4835 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4836 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4837 }
4838 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4839 {
4840 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
4841 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
4842 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
4843 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
4844 }
4845 else
4846 {
4847 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
4848 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
4849 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
4850 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
4851 }
4852 /*Wait for the CRYPEN bit to be cleared*/
4853 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4854 do
4855 {
4856 count-- ;
4857 if (count == 0U)
4858 {
4859 /* Disable the CRYP peripheral clock */
4860 __HAL_CRYP_DISABLE(hcryp);
4861
4862 /* Change state */
4863 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4864 hcryp->State = HAL_CRYP_STATE_READY;
4865
4866 /* Process unlocked */
4867 __HAL_UNLOCK(hcryp);
4868 return HAL_ERROR;
4869 }
4870 }
4871 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4872
4873 /* Select header phase */
4874 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4875
4876 } /* end of if (DoKeyIVConfig == 1U) */
4877
4878 /* Enable interrupts */
4879 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
4880
4881 /* Enable CRYP */
4882 __HAL_CRYP_ENABLE(hcryp);
4883
4884#else /* AES */
4885
4886 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
4887 /* Select header phase */
4888 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4889
4890 /* configured mode and encryption mode */
4891 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4892
4893 /* Set the key */
4894 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4895
4896 /* Set the initialization vector with zero values*/
4897 hcryp->Instance->IVR3 = 0U;
4898 hcryp->Instance->IVR2 = 0U;
4899 hcryp->Instance->IVR1 = 0U;
4900 hcryp->Instance->IVR0 = 0U;
4901
4902 /* Enable interrupts */
4903 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4904 /* Enable the CRYP peripheral */
4905 __HAL_CRYP_ENABLE(hcryp);
4906
4907 /*Write the B0 packet into CRYP_DIN*/
4908 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
4909 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
4910 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
4911 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
4912
4913 } /* end of if (DoKeyIVConfig == 1U) */
4914#endif /* End AES or CRYP */
4915
4916 /* Return function status */
4917 return HAL_OK;
4918}
4926static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4927{
4928 uint32_t wordsize;
4929 __IO uint32_t count = 0U;
4930 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4931#if defined(AES)
4932 uint32_t loopcounter;
4933 uint32_t npblb;
4934 uint32_t lastwordsize;
4935#endif
4936
4937 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4938 {
4939 if (hcryp->KeyIVConfig == 1U)
4940 {
4941 /* If the Key and IV configuration has to be done only once
4942 and if it has already been done, skip it */
4943 DoKeyIVConfig = 0U;
4944 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4945 }
4946 else
4947 {
4948 /* If the Key and IV configuration has to be done only once
4949 and if it has not been done already, do it and set KeyIVConfig
4950 to keep track it won't have to be done again next time */
4951 hcryp->KeyIVConfig = 1U;
4952 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4953 }
4954 }
4955 else
4956 {
4957 hcryp->SizesSum = hcryp->Size;
4958 }
4959
4960 if (DoKeyIVConfig == 1U)
4961 {
4962
4963 /* Reset CrypHeaderCount */
4964 hcryp->CrypHeaderCount = 0U;
4965
4966#if defined(CRYP)
4967
4968 /************************** Init phase **************************************/
4969
4970 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4971
4972 /* Set the key */
4973 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4974
4975 /* Set the initialization vector (IV) with CTR1 information */
4976 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4977 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4978 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4979 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4980
4981 /* Enable the CRYP peripheral */
4982 __HAL_CRYP_ENABLE(hcryp);
4983
4984 /*Write the B0 packet into CRYP_DIN Register*/
4985 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4986 {
4987 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4988 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4989 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4990 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4991 }
4992 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4993 {
4994 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4995 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4996 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4997 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4998 }
4999 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
5000 {
5001 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
5002 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
5003 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
5004 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
5005 }
5006 else
5007 {
5008 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
5009 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
5010 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
5011 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
5012 }
5013
5014 /*Wait for the CRYPEN bit to be cleared*/
5015 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5016 do
5017 {
5018 count-- ;
5019 if (count == 0U)
5020 {
5021 /* Disable the CRYP peripheral clock */
5022 __HAL_CRYP_DISABLE(hcryp);
5023
5024 /* Change state */
5025 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5026 hcryp->State = HAL_CRYP_STATE_READY;
5027
5028 /* Process unlocked */
5029 __HAL_UNLOCK(hcryp);
5030 return HAL_ERROR;
5031 }
5032 }
5033 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
5034
5035#else /* AES */
5036
5037 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
5038 /* Select header phase */
5039 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5040
5041 /* configured encryption mode */
5042 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
5043
5044 /* Set the key */
5045 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5046
5047 /* Set the initialization vector with zero values*/
5048 hcryp->Instance->IVR3 = 0U;
5049 hcryp->Instance->IVR2 = 0U;
5050 hcryp->Instance->IVR1 = 0U;
5051 hcryp->Instance->IVR0 = 0U;
5052
5053 /* Enable the CRYP peripheral */
5054 __HAL_CRYP_ENABLE(hcryp);
5055
5056 /*Write the B0 packet into CRYP_DIN*/
5057 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
5058 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
5059 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
5060 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
5061
5062 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5063 do
5064 {
5065 count-- ;
5066 if (count == 0U)
5067 {
5068 /* Disable the CRYP peripheral clock */
5069 __HAL_CRYP_DISABLE(hcryp);
5070
5071 /* Change state */
5072 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5073 hcryp->State = HAL_CRYP_STATE_READY;
5074
5075 /* Process Unlocked */
5076 __HAL_UNLOCK(hcryp);
5077 return HAL_ERROR;
5078 }
5079 }
5080 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5081 /* Clear CCF flag */
5082 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5083
5084 /* Set the phase */
5085 hcryp->Phase = CRYP_PHASE_PROCESS;
5086
5087 /* From that point the whole message must be processed, first the Header then the payload.
5088 First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
5089
5090 if (hcryp->Init.HeaderSize != 0U)
5091 {
5092 if ((hcryp->Init.HeaderSize % 4U) == 0U)
5093 {
5094 /* HeaderSize %4, no padding */
5095 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
5096 {
5097 /* Write the Input block in the Data Input register */
5098 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5099 hcryp->CrypHeaderCount++ ;
5100 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5101 hcryp->CrypHeaderCount++ ;
5102 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5103 hcryp->CrypHeaderCount++ ;
5104 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5105 hcryp->CrypHeaderCount++ ;
5106
5107 /* wait until the end of computation */
5108 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5109 do
5110 {
5111 count-- ;
5112 if (count == 0U)
5113 {
5114 /* Disable the CRYP peripheral clock */
5115 __HAL_CRYP_DISABLE(hcryp);
5116
5117 /* Change state */
5118 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5119 hcryp->State = HAL_CRYP_STATE_READY;
5120
5121 /* Process Unlocked */
5122 __HAL_UNLOCK(hcryp);
5123 return HAL_ERROR;
5124 }
5125 }
5126 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5127 /* Clear CCF flag */
5128 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5129 }
5130 }
5131 else
5132 {
5133 /*Write Header block in the IN FIFO without last block */
5134 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
5135 {
5136 /* Write the input block in the data input register */
5137 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5138 hcryp->CrypHeaderCount++ ;
5139 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5140 hcryp->CrypHeaderCount++ ;
5141 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5142 hcryp->CrypHeaderCount++ ;
5143 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5144 hcryp->CrypHeaderCount++ ;
5145
5146 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5147 do
5148 {
5149 count-- ;
5150 if (count == 0U)
5151 {
5152 /* Disable the CRYP peripheral clock */
5153 __HAL_CRYP_DISABLE(hcryp);
5154
5155 /* Change state */
5156 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5157 hcryp->State = HAL_CRYP_STATE_READY;
5158
5159 /* Process Unlocked */
5160 __HAL_UNLOCK(hcryp);
5161 return HAL_ERROR;
5162 }
5163 }
5164 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5165 /* Clear CCF flag */
5166 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5167 }
5168 /* Last block optionally pad the data with zeros*/
5169 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
5170 {
5171 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5172 hcryp->CrypHeaderCount++ ;
5173 }
5174 while (loopcounter < 4U)
5175 {
5176 /* Pad the data with zeros to have a complete block */
5177 hcryp->Instance->DINR = 0x0U;
5178 loopcounter++;
5179 }
5180
5181 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5182 do
5183 {
5184 count-- ;
5185 if (count == 0U)
5186 {
5187 /* Disable the CRYP peripheral clock */
5188 __HAL_CRYP_DISABLE(hcryp);
5189
5190 /* Change state */
5191 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5192 hcryp->State = HAL_CRYP_STATE_READY;
5193
5194 /* Process Unlocked */
5195 __HAL_UNLOCK(hcryp);
5196 return HAL_ERROR;
5197 }
5198 }
5199 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5200 /* Clear CCF flag */
5201 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5202 }
5203 }
5204 } /* if (DoKeyIVConfig == 1U) */
5205 /* Then the payload: cleartext payload (not the ciphertext payload).
5206 Write input Data, no output Data to get */
5207 if (hcryp->Size != 0U)
5208 {
5209 if (hcryp->Size >= 16U)
5210 {
5211 if ((hcryp->Size % 16U) == 0U)
5212 {
5213 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
5214 }
5215 else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
5216 {
5217 wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
5218
5219 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
5220 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
5221 (uint32_t)(hcryp->pCrypOutBuffPtr));
5222 }
5223 }
5224 if ((hcryp->Size < 16U) != 0U)
5225 {
5226 /* Compute the number of padding bytes in last block of payload */
5227 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5228
5229 /* Number of valid words (lastwordsize) in last block */
5230 if ((npblb % 4U) == 0U)
5231 {
5232 lastwordsize = (16U - npblb) / 4U;
5233 }
5234 else
5235 {
5236 lastwordsize = ((16U - npblb) / 4U) + 1U;
5237 }
5238 /* Last block optionally pad the data with zeros*/
5239 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
5240 {
5241 /* Write the last input block in the IN FIFO */
5242 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5243 hcryp->CrypInCount++;
5244 }
5245 while (loopcounter < 4U)
5246 {
5247 /* Pad the data with zeros to have a complete block */
5248 hcryp->Instance->DINR = 0U;
5249 loopcounter++;
5250 }
5251 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5252 do
5253 {
5254 count-- ;
5255 if (count == 0U)
5256 {
5257 /* Disable the CRYP peripheral clock */
5258 __HAL_CRYP_DISABLE(hcryp);
5259
5260 /* Change state */
5261 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5262 hcryp->State = HAL_CRYP_STATE_READY;
5263
5264 /* Process Unlocked */
5265 __HAL_UNLOCK(hcryp);
5266 return HAL_ERROR;
5267 }
5268 }
5269 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5270 /* Clear CCF flag */
5271 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5272
5273 /* Process unlocked */
5274 __HAL_UNLOCK(hcryp);
5275
5276 /* Change the CRYP state and phase */
5277 hcryp->State = HAL_CRYP_STATE_READY;
5278 }
5279 }
5280 else
5281 {
5282 /* Process unLocked */
5283 __HAL_UNLOCK(hcryp);
5284
5285 /* Change the CRYP state and phase */
5286 hcryp->State = HAL_CRYP_STATE_READY;
5287 }
5288#endif /* AES */
5289#if defined(CRYP)
5290 /********************* Header phase *****************************************/
5291
5292 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
5293 {
5294 return HAL_ERROR;
5295 }
5296
5297 /******************** Payload phase *****************************************/
5298
5299 /* Set the phase */
5300 hcryp->Phase = CRYP_PHASE_PROCESS;
5301
5302 /* Disable the CRYP peripheral */
5303 __HAL_CRYP_DISABLE(hcryp);
5304
5305 /* Select payload phase once the header phase is performed */
5306 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
5307
5308 } /* if (DoKeyIVConfig == 1U) */
5309 if (hcryp->Size != 0U)
5310 {
5311 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
5312 Workaround is implemented in polling mode, so if last block of
5313 payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
5314 /* Set the input and output addresses and start DMA transfer */
5315 if ((hcryp->Size % 16U) == 0U)
5316 {
5317 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size / 4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
5318 }
5319 else
5320 {
5321 wordsize = (uint32_t)(hcryp->Size) + 16U - ((uint32_t)(hcryp->Size) % 16U) ;
5322
5323 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
5324 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize / 4U,
5325 (uint32_t)(hcryp->pCrypOutBuffPtr));
5326 }
5327 }
5328 else /*Size = 0*/
5329 {
5330 /* Process unlocked */
5331 __HAL_UNLOCK(hcryp);
5332
5333 /* Change the CRYP state and phase */
5334 hcryp->State = HAL_CRYP_STATE_READY;
5335 }
5336#endif /* CRYP */
5337 /* Return function status */
5338 return HAL_OK;
5339}
5340
5347static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
5348{
5349 uint32_t loopcounter;
5350 uint32_t temp[4]; /* Temporary CrypOutBuff */
5351 uint32_t lastwordsize;
5352 uint32_t npblb;
5353 uint32_t i;
5354#if defined(AES)
5355 uint16_t outcount; /* Temporary CrypOutCount Value */
5356#endif /* AES */
5357
5358 /***************************** Payload phase *******************************/
5359
5360#if defined(CRYP)
5361 if (hcryp->Size == 0U)
5362 {
5363 /* Disable interrupts */
5364 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
5365
5366 /* Process unlocked */
5367 __HAL_UNLOCK(hcryp);
5368
5369 /* Change the CRYP state */
5370 hcryp->State = HAL_CRYP_STATE_READY;
5371 }
5372
5373 else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
5374 {
5375 /* Write the input block in the IN FIFO */
5376 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5377 hcryp->CrypInCount++;
5378 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5379 hcryp->CrypInCount++;
5380 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5381 hcryp->CrypInCount++;
5382 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5383 hcryp->CrypInCount++;
5384 if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U))
5385 {
5386 /* Disable interrupts */
5387 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
5388
5389 /* Call the input data transfer complete callback */
5390#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5391 /*Call registered Input complete callback*/
5392 hcryp->InCpltCallback(hcryp);
5393#else
5394 /*Call legacy weak Input complete callback*/
5395 HAL_CRYP_InCpltCallback(hcryp);
5396#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5397 }
5398 if (hcryp->CrypOutCount < (hcryp->Size / 4U))
5399 {
5400 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
5401 for (i = 0U; i < 4U; i++)
5402 {
5403 temp[i] = hcryp->Instance->DOUT;
5404 }
5405 i = 0U;
5406 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
5407 {
5408 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5409 hcryp->CrypOutCount++;
5410 i++;
5411 }
5412 if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
5413 {
5414 /* Disable interrupts */
5415 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
5416
5417 /* Change the CRYP state */
5418 hcryp->State = HAL_CRYP_STATE_READY;
5419
5420 /* Disable CRYP */
5421 __HAL_CRYP_DISABLE(hcryp);
5422
5423 /* Process unlocked */
5424 __HAL_UNLOCK(hcryp);
5425
5426 /* Call output transfer complete callback */
5427#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5428 /*Call registered Output complete callback*/
5429 hcryp->OutCpltCallback(hcryp);
5430#else
5431 /*Call legacy weak Output complete callback*/
5432 HAL_CRYP_OutCpltCallback(hcryp);
5433#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5434 }
5435 }
5436 }
5437 else if ((hcryp->Size % 16U) != 0U)
5438 {
5439 /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
5440 Workaround is implemented in polling mode, so if last block of
5441 payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
5442
5443 /* Compute the number of padding bytes in last block of payload */
5444 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5445
5446 /* Number of valid words (lastwordsize) in last block */
5447 if ((npblb % 4U) == 0U)
5448 {
5449 lastwordsize = (16U - npblb) / 4U;
5450 }
5451 else
5452 {
5453 lastwordsize = ((16U - npblb) / 4U) + 1U;
5454 }
5455
5456 /* Last block optionally pad the data with zeros*/
5457 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5458 {
5459 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5460 hcryp->CrypInCount++;
5461 }
5462 while (loopcounter < 4U)
5463 {
5464 /* Pad the data with zeros to have a complete block */
5465 hcryp->Instance->DIN = 0x0U;
5466 loopcounter++;
5467 }
5468 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
5469
5470 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
5471 {
5472 for (i = 0U; i < 4U; i++)
5473 {
5474 temp[i] = hcryp->Instance->DOUT;
5475 }
5476 if (((hcryp->Size) / 4U) == 0U)
5477 {
5478 for (i = 0U; i < ((uint32_t)(hcryp->Size) % 4U); i++)
5479 {
5480 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5481 hcryp->CrypOutCount++;
5482 }
5483 }
5484 i = 0x0U;
5485 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
5486 {
5487 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5488 hcryp->CrypOutCount++;
5489 i++;
5490 }
5491 }
5492 if (hcryp->CrypOutCount >= (hcryp->Size / 4U))
5493 {
5494 /* Disable interrupts */
5495 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
5496
5497 /* Change the CRYP peripheral state */
5498 hcryp->State = HAL_CRYP_STATE_READY;
5499
5500 /* Process unlocked */
5501 __HAL_UNLOCK(hcryp);
5502
5503 /* Call output transfer complete callback */
5504#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5505 /*Call registered Output complete callback*/
5506 hcryp->OutCpltCallback(hcryp);
5507#else
5508 /*Call legacy weak Output complete callback*/
5509 HAL_CRYP_OutCpltCallback(hcryp);
5510#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5511 }
5512 }
5513 else
5514 {
5515 /* Nothing to do */
5516 }
5517#else /* AES */
5518
5519 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
5520 for (i = 0U; i < 4U; i++)
5521 {
5522 temp[i] = hcryp->Instance->DOUTR;
5523 }
5524 i = 0U;
5525 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
5526 {
5527 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5528 hcryp->CrypOutCount++;
5529 i++;
5530 }
5531 /*Temporary CrypOutCount Value*/
5532 outcount = hcryp->CrypOutCount;
5533
5534 if ((hcryp->CrypOutCount >= (hcryp->Size / 4U)) && ((outcount * 4U) >= hcryp->Size))
5535 {
5536 /* Disable computation complete flag and errors interrupts */
5537 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
5538
5539 /* Change the CRYP state */
5540 hcryp->State = HAL_CRYP_STATE_READY;
5541
5542 /* Process unlocked */
5543 __HAL_UNLOCK(hcryp);
5544
5545 /* Call output transfer complete callback */
5546#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5547 /*Call registered Output complete callback*/
5548 hcryp->OutCpltCallback(hcryp);
5549#else
5550 /*Call legacy weak Output complete callback*/
5551 HAL_CRYP_OutCpltCallback(hcryp);
5552#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5553 }
5554
5555 else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
5556 {
5557 /* Write the input block in the IN FIFO */
5558 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5559 hcryp->CrypInCount++;
5560 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5561 hcryp->CrypInCount++;
5562 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5563 hcryp->CrypInCount++;
5564 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5565 hcryp->CrypInCount++;
5566 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
5567 {
5568 /* Call Input transfer complete callback */
5569#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5570 /*Call registered Input complete callback*/
5571 hcryp->InCpltCallback(hcryp);
5572#else
5573 /*Call legacy weak Input complete callback*/
5574 HAL_CRYP_InCpltCallback(hcryp);
5575#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5576 }
5577 }
5578 else /* Last block of payload < 128bit*/
5579 {
5580 /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
5581 generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of
5582 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */
5583
5584 /* Compute the number of padding bytes in last block of payload */
5585 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5586
5587 /* Number of valid words (lastwordsize) in last block */
5588 if ((npblb % 4U) == 0U)
5589 {
5590 lastwordsize = (16U - npblb) / 4U;
5591 }
5592 else
5593 {
5594 lastwordsize = ((16U - npblb) / 4U) + 1U;
5595 }
5596
5597 /* Last block optionally pad the data with zeros*/
5598 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5599 {
5600 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5601 hcryp->CrypInCount++;
5602 }
5603 while (loopcounter < 4U)
5604 {
5605 /* pad the data with zeros to have a complete block */
5606 hcryp->Instance->DINR = 0x0U;
5607 loopcounter++;
5608 }
5609 }
5610#endif /* AES */
5611
5612}
5613
5614
5622static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
5623{
5624 uint32_t loopcounter;
5625 uint32_t size_in_bytes;
5626 uint32_t tmp;
5627 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
5628 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
5629 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
5630
5631 /***************************** Header phase for GCM/GMAC or CCM *********************************/
5632
5633 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
5634 {
5635 size_in_bytes = hcryp->Init.HeaderSize * 4U;
5636 }
5637 else
5638 {
5639 size_in_bytes = hcryp->Init.HeaderSize;
5640 }
5641
5642 if (size_in_bytes != 0U)
5643 {
5644
5645#if defined(CRYP)
5646
5647 /* Select header phase */
5648 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5649
5650 /* Enable the CRYP peripheral */
5651 __HAL_CRYP_ENABLE(hcryp);
5652
5653 if ((size_in_bytes % 16U) == 0U)
5654 {
5655 /* HeaderSize %4, no padding */
5656 for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
5657 {
5658 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5659 hcryp->CrypHeaderCount++ ;
5660 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5661 hcryp->CrypHeaderCount++ ;
5662 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5663 hcryp->CrypHeaderCount++ ;
5664 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5665 hcryp->CrypHeaderCount++ ;
5666
5667 /* Wait for IFEM to be raised */
5668 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5669 {
5670 /* Disable the CRYP peripheral clock */
5671 __HAL_CRYP_DISABLE(hcryp);
5672
5673 /* Change state */
5674 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5675 hcryp->State = HAL_CRYP_STATE_READY;
5676
5677 /* Process unlocked */
5678 __HAL_UNLOCK(hcryp);
5679 return HAL_ERROR;
5680 }
5681 }
5682 }
5683 else
5684 {
5685 /*Write header block in the IN FIFO without last block */
5686 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
5687 {
5688 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5689 hcryp->CrypHeaderCount++ ;
5690 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5691 hcryp->CrypHeaderCount++ ;
5692 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5693 hcryp->CrypHeaderCount++ ;
5694 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5695 hcryp->CrypHeaderCount++ ;
5696
5697 /* Wait for IFEM to be raised */
5698 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5699 {
5700 /* Disable the CRYP peripheral clock */
5701 __HAL_CRYP_DISABLE(hcryp);
5702
5703 /* Change state */
5704 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5705 hcryp->State = HAL_CRYP_STATE_READY;
5706
5707 /* Process unlocked */
5708 __HAL_UNLOCK(hcryp);
5709 return HAL_ERROR;
5710 }
5711 }
5712 /* Last block optionally pad the data with zeros*/
5713 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
5714 {
5715 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5716 hcryp->CrypHeaderCount++ ;
5717 }
5718 /* If the header size is a multiple of words */
5719 if ((size_in_bytes % 4U) == 0U)
5720 {
5721 /* Pad the data with zeros to have a complete block */
5722 while (loopcounter < 4U)
5723 {
5724 hcryp->Instance->DIN = 0x0U;
5725 loopcounter++;
5726 }
5727 }
5728 else
5729 {
5730 /* Enter last bytes, padded with zeroes */
5731 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5732 tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
5733 hcryp->Instance->DIN = tmp;
5734 loopcounter++;
5735 /* Pad the data with zeros to have a complete block */
5736 while (loopcounter < 4U)
5737 {
5738 hcryp->Instance->DIN = 0x0U;
5739 loopcounter++;
5740 }
5741 }
5742 /* Wait for CCF IFEM to be raised */
5743 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5744 {
5745 /* Disable the CRYP peripheral clock */
5746 __HAL_CRYP_DISABLE(hcryp);
5747
5748 /* Change state */
5749 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5750 hcryp->State = HAL_CRYP_STATE_READY;
5751
5752 /* Process unlocked */
5753 __HAL_UNLOCK(hcryp);
5754 return HAL_ERROR;
5755 }
5756 }
5757 /* Wait until the complete message has been processed */
5758 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
5759 {
5760 /* Disable the CRYP peripheral clock */
5761 __HAL_CRYP_DISABLE(hcryp);
5762
5763 /* Change state */
5764 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5765 hcryp->State = HAL_CRYP_STATE_READY;
5766
5767 /* Process unlocked & return error */
5768 __HAL_UNLOCK(hcryp);
5769 return HAL_ERROR;
5770 }
5771
5772#else /* AES */
5773
5774 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5775 {
5776 /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/
5777 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5778
5779 /* Select header phase */
5780 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5781
5782 /* Enable the CRYP peripheral */
5783 __HAL_CRYP_ENABLE(hcryp);
5784
5785 }
5786 /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
5787 if ((size_in_bytes % 16U) == 0U)
5788 {
5789 /* No padding */
5790 for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
5791 {
5792 /* Write the input block in the data input register */
5793 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5794 hcryp->CrypHeaderCount++ ;
5795 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5796 hcryp->CrypHeaderCount++ ;
5797 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5798 hcryp->CrypHeaderCount++ ;
5799 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5800 hcryp->CrypHeaderCount++ ;
5801
5802 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5803 {
5804 /* Disable the CRYP peripheral clock */
5805 __HAL_CRYP_DISABLE(hcryp);
5806
5807 /* Change state */
5808 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5809 hcryp->State = HAL_CRYP_STATE_READY;
5810
5811 /* Process unlocked */
5812 __HAL_UNLOCK(hcryp);
5813 return HAL_ERROR;
5814 }
5815 /* Clear CCF flag */
5816 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5817 }
5818 }
5819 else
5820 {
5821 /*Write header block in the IN FIFO without last block */
5822 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
5823 {
5824 /* Write the input block in the data input register */
5825 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5826 hcryp->CrypHeaderCount++ ;
5827 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5828 hcryp->CrypHeaderCount++ ;
5829 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5830 hcryp->CrypHeaderCount++ ;
5831 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5832 hcryp->CrypHeaderCount++ ;
5833
5834 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5835 {
5836 /* Disable the CRYP peripheral clock */
5837 __HAL_CRYP_DISABLE(hcryp);
5838
5839 /* Change state */
5840 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5841 hcryp->State = HAL_CRYP_STATE_READY;
5842
5843 /* Process unlocked */
5844 __HAL_UNLOCK(hcryp);
5845 return HAL_ERROR;
5846 }
5847 /* Clear CCF flag */
5848 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5849 }
5850 /* Write last complete words */
5851 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
5852 {
5853 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5854 hcryp->CrypHeaderCount++ ;
5855 }
5856 /* If the header size is a multiple of words */
5857 if ((size_in_bytes % 4U) == 0U)
5858 {
5859 /* Pad the data with zeros to have a complete block */
5860 while (loopcounter < 4U)
5861 {
5862 hcryp->Instance->DINR = 0x0U;
5863 loopcounter++;
5864 }
5865 }
5866 else
5867 {
5868 /* Enter last bytes, padded with zeroes */
5869 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5870 tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
5871 hcryp->Instance->DINR = tmp;
5872 loopcounter++;
5873 /* Pad the data with zeros to have a complete block */
5874 while (loopcounter < 4U)
5875 {
5876 hcryp->Instance->DINR = 0x0U;
5877 loopcounter++;
5878 }
5879 }
5880
5881 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5882 {
5883 /* Disable the CRYP peripheral clock */
5884 __HAL_CRYP_DISABLE(hcryp);
5885
5886 /* Change state */
5887 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5888 hcryp->State = HAL_CRYP_STATE_READY;
5889
5890 /* Process unlocked */
5891 __HAL_UNLOCK(hcryp);
5892 return HAL_ERROR;
5893 }
5894 /* Clear CCF flag */
5895 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5896 }
5897#endif /* End AES or CRYP */
5898 }
5899 else
5900 {
5901#if defined(AES)
5902 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5903 {
5904 /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
5905 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5906
5907 /* Select header phase */
5908 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5909
5910 /* Enable the CRYP peripheral */
5911 __HAL_CRYP_ENABLE(hcryp);
5912 }
5913#endif /* AES */
5914 }
5915 /* Return function status */
5916 return HAL_OK;
5917}
5918
5925static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
5926{
5927 __IO uint32_t count = 0U;
5928 uint32_t loopcounter;
5929 uint32_t headersize_in_bytes;
5930 uint32_t tmp;
5931 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
5932 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
5933 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
5934
5935 /***************************** Header phase for GCM/GMAC or CCM *********************************/
5936 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
5937 {
5938 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
5939 }
5940 else
5941 {
5942 headersize_in_bytes = hcryp->Init.HeaderSize;
5943 }
5944
5945 if (headersize_in_bytes != 0U)
5946 {
5947
5948#if defined(CRYP)
5949
5950 /* Select header phase */
5951 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5952
5953 /* Enable the CRYP peripheral */
5954 __HAL_CRYP_ENABLE(hcryp);
5955
5956 if ((headersize_in_bytes % 16U) == 0U)
5957 {
5958 /* HeaderSize %4, no padding */
5959 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
5960 {
5961 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5962 hcryp->CrypHeaderCount++ ;
5963 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5964 hcryp->CrypHeaderCount++ ;
5965 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5966 hcryp->CrypHeaderCount++ ;
5967 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5968 hcryp->CrypHeaderCount++ ;
5969
5970 /* Wait for IFEM to be raised */
5971 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5972 do
5973 {
5974 count-- ;
5975 if (count == 0U)
5976 {
5977 /* Disable the CRYP peripheral clock */
5978 __HAL_CRYP_DISABLE(hcryp);
5979
5980 /* Change state */
5981 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5982 hcryp->State = HAL_CRYP_STATE_READY;
5983
5984 /* Process unlocked */
5985 __HAL_UNLOCK(hcryp);
5986 return HAL_ERROR;
5987 }
5988 }
5989 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
5990 }
5991 }
5992 else
5993 {
5994 /*Write header block in the IN FIFO without last block */
5995 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
5996 {
5997 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5998 hcryp->CrypHeaderCount++ ;
5999 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6000 hcryp->CrypHeaderCount++ ;
6001 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6002 hcryp->CrypHeaderCount++ ;
6003 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6004 hcryp->CrypHeaderCount++ ;
6005
6006 /* Wait for IFEM to be raised */
6007 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6008 do
6009 {
6010 count-- ;
6011 if (count == 0U)
6012 {
6013 /* Disable the CRYP peripheral clock */
6014 __HAL_CRYP_DISABLE(hcryp);
6015
6016 /* Change state */
6017 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6018 hcryp->State = HAL_CRYP_STATE_READY;
6019
6020 /* Process unlocked */
6021 __HAL_UNLOCK(hcryp);
6022 return HAL_ERROR;
6023 }
6024 }
6025 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
6026 }
6027 /* Last block optionally pad the data with zeros*/
6028 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
6029 {
6030 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6031 hcryp->CrypHeaderCount++ ;
6032 }
6033 /* If the header size is a multiple of words */
6034 if ((headersize_in_bytes % 4U) == 0U)
6035 {
6036 /* Pad the data with zeros to have a complete block */
6037 while (loopcounter < 4U)
6038 {
6039 hcryp->Instance->DIN = 0x0U;
6040 loopcounter++;
6041 }
6042 }
6043 else
6044 {
6045 /* Enter last bytes, padded with zeroes */
6046 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6047 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6048 hcryp->Instance->DIN = tmp;
6049 loopcounter++;
6050 /* Pad the data with zeros to have a complete block */
6051 while (loopcounter < 4U)
6052 {
6053 hcryp->Instance->DIN = 0x0U;
6054 loopcounter++;
6055 }
6056 }
6057 /* Wait for IFEM to be raised */
6058 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6059 do
6060 {
6061 count-- ;
6062 if (count == 0U)
6063 {
6064 /* Disable the CRYP peripheral clock */
6065 __HAL_CRYP_DISABLE(hcryp);
6066
6067 /* Change state */
6068 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6069 hcryp->State = HAL_CRYP_STATE_READY;
6070
6071 /* Process unlocked */
6072 __HAL_UNLOCK(hcryp);
6073 return HAL_ERROR;
6074 }
6075 }
6076 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
6077 }
6078 /* Wait until the complete message has been processed */
6079 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6080 do
6081 {
6082 count-- ;
6083 if (count == 0U)
6084 {
6085 /* Disable the CRYP peripheral clock */
6086 __HAL_CRYP_DISABLE(hcryp);
6087
6088 /* Change state */
6089 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6090 hcryp->State = HAL_CRYP_STATE_READY;
6091
6092 /* Process unlocked */
6093 __HAL_UNLOCK(hcryp);
6094 return HAL_ERROR;
6095 }
6096 }
6097 while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
6098
6099#else /* AES */
6100
6101 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6102 {
6103 /* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
6104 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
6105
6106 /* Select header phase */
6107 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
6108
6109 /* Enable the CRYP peripheral */
6110 __HAL_CRYP_ENABLE(hcryp);
6111 }
6112 if ((headersize_in_bytes % 16U) == 0U)
6113 {
6114 /* HeaderSize %4, no padding */
6115 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
6116 {
6117 /* Write the input block in the data input register */
6118 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6119 hcryp->CrypHeaderCount++ ;
6120 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6121 hcryp->CrypHeaderCount++ ;
6122 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6123 hcryp->CrypHeaderCount++ ;
6124 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6125 hcryp->CrypHeaderCount++ ;
6126
6127 /*Wait on CCF flag*/
6128 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6129 do
6130 {
6131 count-- ;
6132 if (count == 0U)
6133 {
6134 /* Disable the CRYP peripheral clock */
6135 __HAL_CRYP_DISABLE(hcryp);
6136
6137 /* Change state */
6138 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6139 hcryp->State = HAL_CRYP_STATE_READY;
6140
6141 /* Process unlocked */
6142 __HAL_UNLOCK(hcryp);
6143 return HAL_ERROR;
6144 }
6145 }
6146 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6147
6148 /* Clear CCF flag */
6149 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6150 }
6151 }
6152 else
6153 {
6154 /*Write header block in the IN FIFO without last block */
6155 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
6156 {
6157 /* Write the Input block in the Data Input register */
6158 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6159 hcryp->CrypHeaderCount++ ;
6160 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6161 hcryp->CrypHeaderCount++ ;
6162 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6163 hcryp->CrypHeaderCount++ ;
6164 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6165 hcryp->CrypHeaderCount++ ;
6166
6167 /*Wait on CCF flag*/
6168 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6169 do
6170 {
6171 count-- ;
6172 if (count == 0U)
6173 {
6174 /* Disable the CRYP peripheral clock */
6175 __HAL_CRYP_DISABLE(hcryp);
6176
6177 /* Change state */
6178 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6179 hcryp->State = HAL_CRYP_STATE_READY;
6180
6181 /* Process unlocked */
6182 __HAL_UNLOCK(hcryp);
6183 return HAL_ERROR;
6184 }
6185 }
6186 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6187
6188 /* Clear CCF flag */
6189 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6190 }
6191 /* Last block optionally pad the data with zeros*/
6192 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
6193 {
6194 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6195 hcryp->CrypHeaderCount++ ;
6196 }
6197 /* If the header size is a multiple of words */
6198 if ((headersize_in_bytes % 4U) == 0U)
6199 {
6200 /* Pad the data with zeros to have a complete block */
6201 while (loopcounter < 4U)
6202 {
6203 hcryp->Instance->DINR = 0x0U;
6204 loopcounter++;
6205 }
6206 }
6207 else
6208 {
6209 /* Enter last bytes, padded with zeroes */
6210 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6211 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6212 hcryp->Instance->DINR = tmp;
6213 loopcounter++;
6214 /* Pad the data with zeros to have a complete block */
6215 while (loopcounter < 4U)
6216 {
6217 hcryp->Instance->DINR = 0x0U;
6218 loopcounter++;
6219 }
6220 }
6221 /*Wait on CCF flag*/
6222 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6223 do
6224 {
6225 count-- ;
6226 if (count == 0U)
6227 {
6228 /* Disable the CRYP peripheral clock */
6229 __HAL_CRYP_DISABLE(hcryp);
6230
6231 /* Change state */
6232 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6233 hcryp->State = HAL_CRYP_STATE_READY;
6234
6235 /* Process unlocked */
6236 __HAL_UNLOCK(hcryp);
6237 return HAL_ERROR;
6238 }
6239 }
6240 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6241
6242 /* Clear CCF flag */
6243 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6244 }
6245#endif /* End AES or CRYP */
6246 }
6247 else
6248 {
6249#if defined(AES)
6250 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6251 {
6252 /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
6253 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
6254
6255 /* Select header phase */
6256 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
6257
6258 /* Enable the CRYP peripheral */
6259 __HAL_CRYP_ENABLE(hcryp);
6260 }
6261#endif /* AES */
6262 }
6263 /* Return function status */
6264 return HAL_OK;
6265}
6266
6273static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
6274{
6275 uint32_t loopcounter;
6276#if defined(AES)
6277 uint32_t lastwordsize;
6278 uint32_t npblb;
6279#endif
6280 uint32_t headersize_in_bytes;
6281 uint32_t tmp;
6282 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
6283 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
6284 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
6285
6286 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
6287 {
6288 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
6289 }
6290 else
6291 {
6292 headersize_in_bytes = hcryp->Init.HeaderSize;
6293 }
6294
6295 /***************************** Header phase *********************************/
6296
6297#if defined(CRYP)
6298 if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
6299 {
6300 /* Disable interrupts */
6301 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
6302
6303 /* Disable the CRYP peripheral */
6304 __HAL_CRYP_DISABLE(hcryp);
6305
6306 /* Set the phase */
6307 hcryp->Phase = CRYP_PHASE_PROCESS;
6308
6309 /* Select payload phase once the header phase is performed */
6310 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
6311
6312 /* Enable Interrupts */
6313 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
6314
6315 /* Enable the CRYP peripheral */
6316 __HAL_CRYP_ENABLE(hcryp);
6317 }
6318 else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
6319
6320 {
6321 /* HeaderSize %4, no padding */
6322 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6323 hcryp->CrypHeaderCount++ ;
6324 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6325 hcryp->CrypHeaderCount++ ;
6326 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6327 hcryp->CrypHeaderCount++ ;
6328 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6329 hcryp->CrypHeaderCount++ ;
6330 }
6331 else
6332 {
6333 /* Last block optionally pad the data with zeros*/
6334 for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
6335 {
6336 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6337 hcryp->CrypHeaderCount++ ;
6338 }
6339 if ((headersize_in_bytes % 4U) == 0U)
6340 {
6341 /* Pad the data with zeros to have a complete block */
6342 while (loopcounter < 4U)
6343 {
6344 hcryp->Instance->DIN = 0x0U;
6345 loopcounter++;
6346 hcryp->CrypHeaderCount++;
6347 }
6348 }
6349 else
6350 {
6351 /* Enter last bytes, padded with zeros */
6352 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6353 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6354 hcryp->Instance->DIN = tmp;
6355 loopcounter++;
6356 hcryp->CrypHeaderCount++;
6357 /* Pad the data with zeros to have a complete block */
6358 while (loopcounter < 4U)
6359 {
6360 hcryp->Instance->DIN = 0x0U;
6361 loopcounter++;
6362 hcryp->CrypHeaderCount++;
6363 }
6364 }
6365 }
6366#else /* AES */
6367
6368 if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
6369 {
6370 /* Set the phase */
6371 hcryp->Phase = CRYP_PHASE_PROCESS;
6372
6373 /* Payload phase not supported in CCM AES2 */
6374 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6375 {
6376 /* Select payload phase once the header phase is performed */
6377 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
6378 }
6379 if (hcryp->Init.Algorithm == CRYP_AES_CCM)
6380 {
6381 /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
6382 hcryp->CrypHeaderCount++;
6383 }
6384 /* Write the payload Input block in the IN FIFO */
6385 if (hcryp->Size == 0U)
6386 {
6387 /* Disable interrupts */
6388 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
6389
6390 /* Change the CRYP state */
6391 hcryp->State = HAL_CRYP_STATE_READY;
6392
6393 /* Process unlocked */
6394 __HAL_UNLOCK(hcryp);
6395 }
6396 else if (hcryp->Size >= 16U)
6397 {
6398 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6399 hcryp->CrypInCount++;
6400 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6401 hcryp->CrypInCount++;
6402 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6403 hcryp->CrypInCount++;
6404 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6405 hcryp->CrypInCount++;
6406
6407 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
6408 {
6409 /* Call the input data transfer complete callback */
6410#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6411 /*Call registered Input complete callback*/
6412 hcryp->InCpltCallback(hcryp);
6413#else
6414 /*Call legacy weak Input complete callback*/
6415 HAL_CRYP_InCpltCallback(hcryp);
6416#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6417 }
6418 }
6419 else /* Size < 4 words : first block is the last block*/
6420 {
6421 /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
6422 generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of
6423 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
6424
6425 /* Compute the number of padding bytes in last block of payload */
6426 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6427
6428 /* Number of valid words (lastwordsize) in last block */
6429 if ((npblb % 4U) == 0U)
6430 {
6431 lastwordsize = (16U - npblb) / 4U;
6432 }
6433 else
6434 {
6435 lastwordsize = ((16U - npblb) / 4U) + 1U;
6436 }
6437
6438 /* Last block optionally pad the data with zeros*/
6439 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
6440 {
6441 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6442 hcryp->CrypInCount++;
6443 }
6444 while (loopcounter < 4U)
6445 {
6446 /* Pad the data with zeros to have a complete block */
6447 hcryp->Instance->DINR = 0x0U;
6448 loopcounter++;
6449 }
6450 }
6451 }
6452 else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
6453 {
6454 /* Write the input block in the IN FIFO */
6455 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6456 hcryp->CrypHeaderCount++;
6457 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6458 hcryp->CrypHeaderCount++;
6459 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6460 hcryp->CrypHeaderCount++;
6461 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6462 hcryp->CrypHeaderCount++;
6463 }
6464 else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
6465 {
6466 /* Last block optionally pad the data with zeros*/
6467 for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
6468 {
6469 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6470 hcryp->CrypHeaderCount++ ;
6471 }
6472 /* If the header size is a multiple of words */
6473 if ((headersize_in_bytes % 4U) == 0U)
6474 {
6475 /* Pad the data with zeros to have a complete block */
6476 while (loopcounter < 4U)
6477 {
6478 hcryp->Instance->DINR = 0x0U;
6479 loopcounter++;
6480 hcryp->CrypHeaderCount++;
6481 }
6482 }
6483 else
6484 {
6485 /* Enter last bytes, padded with zeros */
6486 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6487 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6488 hcryp->Instance->DINR = tmp;
6489 loopcounter++;
6490 hcryp->CrypHeaderCount++;
6491 /* Pad the data with zeros to have a complete block */
6492 while (loopcounter < 4U)
6493 {
6494 hcryp->Instance->DINR = 0x0U;
6495 loopcounter++;
6496 hcryp->CrypHeaderCount++;
6497 }
6498 }
6499 }
6500#endif /* End AES or CRYP */
6501}
6502
6503
6511static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6512{
6513 uint32_t lastwordsize;
6514 uint32_t npblb;
6515#if defined(CRYP)
6516 uint32_t iv1temp;
6517 uint32_t temp[4] = {0};
6518 uint32_t temp2[4] = {0};
6519#endif /* CRYP */
6520 uint32_t intermediate_data[4] = {0};
6521 uint32_t index;
6522
6523 /* Compute the number of padding bytes in last block of payload */
6524 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6525
6526 /* Number of valid words (lastwordsize) in last block */
6527 if ((npblb % 4U) == 0U)
6528 {
6529 lastwordsize = (16U - npblb) / 4U;
6530 }
6531 else
6532 {
6533 lastwordsize = ((16U - npblb) / 4U) + 1U;
6534 }
6535
6536#if defined(CRYP)
6537
6538 /* Workaround 2, case GCM encryption */
6539 if (hcryp->Init.Algorithm == CRYP_AES_GCM)
6540 {
6541 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
6542 {
6543 /*Workaround in order to properly compute authentication tags while doing
6544 a GCM encryption with the last block of payload size inferior to 128 bits*/
6545 /* Disable CRYP to start the final phase */
6546 __HAL_CRYP_DISABLE(hcryp);
6547
6548 /*Update CRYP_IV1R register and ALGOMODE*/
6549 hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R) - 1U);
6550 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
6551
6552 /* Enable CRYP to start the final phase */
6553 __HAL_CRYP_ENABLE(hcryp);
6554 }
6555 /* Last block optionally pad the data with zeros*/
6556 for (index = 0; index < lastwordsize; index ++)
6557 {
6558 /* Write the last input block in the IN FIFO */
6559 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6560 hcryp->CrypInCount++;
6561 }
6562 while (index < 4U)
6563 {
6564 /* Pad the data with zeros to have a complete block */
6565 hcryp->Instance->DIN = 0U;
6566 index++;
6567 }
6568 /* Wait for OFNE flag to be raised */
6569 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6570 {
6571 /* Disable the CRYP peripheral clock */
6572 __HAL_CRYP_DISABLE(hcryp);
6573
6574 /* Change state */
6575 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6576 hcryp->State = HAL_CRYP_STATE_READY;
6577
6578 /* Process Unlocked */
6579 __HAL_UNLOCK(hcryp);
6580#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6581 /*Call registered error callback*/
6582 hcryp->ErrorCallback(hcryp);
6583#else
6584 /*Call legacy weak error callback*/
6585 HAL_CRYP_ErrorCallback(hcryp);
6586#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6587 }
6588 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6589 {
6590 for (index = 0U; index < 4U; index++)
6591 {
6592 /* Read the output block from the output FIFO */
6593 intermediate_data[index] = hcryp->Instance->DOUT;
6594
6595 /* Intermediate data buffer to be used in for the workaround*/
6596 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6597 hcryp->CrypOutCount++;
6598 }
6599 }
6600
6601 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
6602 {
6603 /*workaround in order to properly compute authentication tags while doing
6604 a GCM encryption with the last block of payload size inferior to 128 bits*/
6605 /* Change the AES mode to GCM mode and Select Final phase */
6606 /* configured CHMOD GCM */
6607 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
6608
6609 /* configured final phase */
6610 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
6611
6612 if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B)
6613 {
6614 if ((npblb % 4U) == 1U)
6615 {
6616 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6617 }
6618 if ((npblb % 4U) == 2U)
6619 {
6620 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6621 }
6622 if ((npblb % 4U) == 3U)
6623 {
6624 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6625 }
6626 }
6627 else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B)
6628 {
6629 if ((npblb % 4U) == 1U)
6630 {
6631 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
6632 }
6633 if ((npblb % 4U) == 2U)
6634 {
6635 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
6636 }
6637 if ((npblb % 4U) == 3U)
6638 {
6639 intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
6640 }
6641 }
6642 else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B)
6643 {
6644 if ((npblb % 4U) == 1U)
6645 {
6646 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
6647 }
6648 if ((npblb % 4U) == 2U)
6649 {
6650 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
6651 }
6652 if ((npblb % 4U) == 3U)
6653 {
6654 intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
6655 }
6656 }
6657 else /*CRYP_DATATYPE_1B*/
6658 {
6659 if ((npblb % 4U) == 1U)
6660 {
6661 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
6662 }
6663 if ((npblb % 4U) == 2U)
6664 {
6665 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
6666 }
6667 if ((npblb % 4U) == 3U)
6668 {
6669 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
6670 }
6671 }
6672 for (index = 0U; index < lastwordsize; index ++)
6673 {
6674 /*Write the intermediate_data in the IN FIFO */
6675 hcryp->Instance->DIN = intermediate_data[index];
6676 }
6677 while (index < 4U)
6678 {
6679 /* Pad the data with zeros to have a complete block */
6680 hcryp->Instance->DIN = 0x0U;
6681 index++;
6682 }
6683 /* Wait for OFNE flag to be raised */
6684 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6685 {
6686 /* Disable the CRYP peripheral clock */
6687 __HAL_CRYP_DISABLE(hcryp);
6688
6689 /* Change state */
6690 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6691 hcryp->State = HAL_CRYP_STATE_READY;
6692
6693 /* Process unlocked */
6694 __HAL_UNLOCK(hcryp);
6695#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6696 /*Call registered error callback*/
6697 hcryp->ErrorCallback(hcryp);
6698#else
6699 /*Call legacy weak error callback*/
6700 HAL_CRYP_ErrorCallback(hcryp);
6701#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6702 }
6703
6704 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6705 {
6706 for (index = 0U; index < 4U; index++)
6707 {
6708 intermediate_data[index] = hcryp->Instance->DOUT;
6709 }
6710 }
6711 }
6712 } /* End of GCM encryption */
6713 else
6714 {
6715 /* Workaround 2, case CCM decryption, in order to properly compute
6716 authentication tags while doing a CCM decryption with the last block
6717 of payload size inferior to 128 bits*/
6718
6719 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
6720 {
6721 iv1temp = hcryp->Instance->CSGCMCCM7R;
6722
6723 /* Disable CRYP to start the final phase */
6724 __HAL_CRYP_DISABLE(hcryp);
6725
6726 temp[0] = hcryp->Instance->CSGCMCCM0R;
6727 temp[1] = hcryp->Instance->CSGCMCCM1R;
6728 temp[2] = hcryp->Instance->CSGCMCCM2R;
6729 temp[3] = hcryp->Instance->CSGCMCCM3R;
6730
6731 hcryp->Instance->IV1RR = iv1temp;
6732
6733 /* Configured CHMOD CTR */
6734 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
6735
6736 /* Enable CRYP to start the final phase */
6737 __HAL_CRYP_ENABLE(hcryp);
6738 }
6739 /* Last block optionally pad the data with zeros*/
6740 for (index = 0; index < lastwordsize; index ++)
6741 {
6742 /* Write the last Input block in the IN FIFO */
6743 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6744 hcryp->CrypInCount++;
6745 }
6746 while (index < 4U)
6747 {
6748 /* Pad the data with zeros to have a complete block */
6749 hcryp->Instance->DIN = 0U;
6750 index++;
6751 }
6752 /* Wait for OFNE flag to be raised */
6753 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6754 {
6755 /* Disable the CRYP peripheral clock */
6756 __HAL_CRYP_DISABLE(hcryp);
6757
6758 /* Change state */
6759 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6760 hcryp->State = HAL_CRYP_STATE_READY;
6761
6762 /* Process Unlocked */
6763 __HAL_UNLOCK(hcryp);
6764#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6765 /*Call registered error callback*/
6766 hcryp->ErrorCallback(hcryp);
6767#else
6768 /*Call legacy weak error callback*/
6769 HAL_CRYP_ErrorCallback(hcryp);
6770#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6771 }
6772
6773 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6774 {
6775 for (index = 0U; index < 4U; index++)
6776 {
6777 /* Read the Output block from the Output FIFO */
6778 intermediate_data[index] = hcryp->Instance->DOUT;
6779
6780 /*intermediate data buffer to be used in for the workaround*/
6781 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6782 hcryp->CrypOutCount++;
6783 }
6784 }
6785
6786 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
6787 {
6788 temp2[0] = hcryp->Instance->CSGCMCCM0R;
6789 temp2[1] = hcryp->Instance->CSGCMCCM1R;
6790 temp2[2] = hcryp->Instance->CSGCMCCM2R;
6791 temp2[3] = hcryp->Instance->CSGCMCCM3R;
6792
6793 /* configured CHMOD CCM */
6794 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
6795
6796 /* configured Header phase */
6797 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
6798
6799 /*set to zero the bits corresponding to the padded bits*/
6800 for (index = lastwordsize; index < 4U; index ++)
6801 {
6802 intermediate_data[index] = 0U;
6803 }
6804 if ((npblb % 4U) == 1U)
6805 {
6806 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6807 }
6808 if ((npblb % 4U) == 2U)
6809 {
6810 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6811 }
6812 if ((npblb % 4U) == 3U)
6813 {
6814 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6815 }
6816 for (index = 0U; index < 4U ; index ++)
6817 {
6818 intermediate_data[index] ^= temp[index];
6819 intermediate_data[index] ^= temp2[index];
6820 }
6821 for (index = 0U; index < 4U; index ++)
6822 {
6823 /* Write the last Input block in the IN FIFO */
6824 hcryp->Instance->DIN = intermediate_data[index] ;
6825 }
6826
6827 /* Wait for BUSY flag to be raised */
6828 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
6829 {
6830 /* Disable the CRYP peripheral clock */
6831 __HAL_CRYP_DISABLE(hcryp);
6832
6833 /* Change state */
6834 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6835 hcryp->State = HAL_CRYP_STATE_READY;
6836
6837 /* Process Unlocked */
6838 __HAL_UNLOCK(hcryp);
6839#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6840 /*Call registered error callback*/
6841 hcryp->ErrorCallback(hcryp);
6842#else
6843 /*Call legacy weak error callback*/
6844 HAL_CRYP_ErrorCallback(hcryp);
6845#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6846 }
6847 }
6848 } /* End of CCM WKA*/
6849
6850 /* Process Unlocked */
6851 __HAL_UNLOCK(hcryp);
6852
6853#else /* AES */
6854
6855 /*Workaround 2: case GCM encryption, during payload phase and before inserting
6856 the last block of paylaod, which size is inferior to 128 bits */
6857
6858 if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6859 {
6860 /* configured CHMOD CTR */
6861 MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
6862 }
6863 /* last block optionally pad the data with zeros*/
6864 for (index = 0U; index < lastwordsize; index ++)
6865 {
6866 /* Write the last Input block in the IN FIFO */
6867 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6868 hcryp->CrypInCount++;
6869 }
6870 while (index < 4U)
6871 {
6872 /* pad the data with zeros to have a complete block */
6873 hcryp->Instance->DINR = 0U;
6874 index++;
6875 }
6876 /* Wait for CCF flag to be raised */
6877 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6878 {
6879 hcryp->State = HAL_CRYP_STATE_READY;
6880 __HAL_UNLOCK(hcryp);
6881#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6882 /*Call registered error callback*/
6883 hcryp->ErrorCallback(hcryp);
6884#else
6885 /*Call legacy weak error callback*/
6886 HAL_CRYP_ErrorCallback(hcryp);
6887#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6888 }
6889
6890 /* Clear CCF Flag */
6891 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6892
6893 for (index = 0U; index < 4U; index++)
6894 {
6895 /* Read the Output block from the Output FIFO */
6896 intermediate_data[index] = hcryp->Instance->DOUTR;
6897
6898 /*intermediate data buffer to be used in the workaround*/
6899 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6900 hcryp->CrypOutCount++;
6901 }
6902
6903 if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6904 {
6905 /* configured CHMOD GCM */
6906 MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC);
6907
6908 /* Select final phase */
6909 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
6910
6911 if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B)
6912 {
6913 if ((npblb % 4U) == 1U)
6914 {
6915 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6916 }
6917 if ((npblb % 4U) == 2U)
6918 {
6919 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6920 }
6921 if ((npblb % 4U) == 3U)
6922 {
6923 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6924 }
6925 }
6926 else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_8B)
6927 {
6928 if ((npblb % 4U) == 1U)
6929 {
6930 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
6931 }
6932 if ((npblb % 4U) == 2U)
6933 {
6934 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
6935 }
6936 if ((npblb % 4U) == 3U)
6937 {
6938 intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
6939 }
6940 }
6941 else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_16B)
6942 {
6943 if ((npblb % 4U) == 1U)
6944 {
6945 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
6946 }
6947 if ((npblb % 4U) == 2U)
6948 {
6949 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
6950 }
6951 if ((npblb % 4U) == 3U)
6952 {
6953 intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
6954 }
6955 }
6956 else /*CRYP_DATATYPE_1B*/
6957 {
6958 if ((npblb % 4U) == 1U)
6959 {
6960 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
6961 }
6962 if ((npblb % 4U) == 2U)
6963 {
6964 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
6965 }
6966 if ((npblb % 4U) == 3U)
6967 {
6968 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
6969 }
6970 }
6971
6972 /*Write the intermediate_data in the IN FIFO */
6973 for (index = 0U; index < lastwordsize; index ++)
6974 {
6975 hcryp->Instance->DINR = intermediate_data[index];
6976 }
6977 while (index < 4U)
6978 {
6979 /* pad the data with zeros to have a complete block */
6980 hcryp->Instance->DINR = 0U;
6981 index++;
6982 }
6983 /* Wait for CCF flag to be raised */
6984 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6985 {
6986 /* Disable the CRYP peripheral clock */
6987 __HAL_CRYP_DISABLE(hcryp);
6988
6989 /* Change state */
6990 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6991 hcryp->State = HAL_CRYP_STATE_READY;
6992
6993 /* Process Unlocked */
6994 __HAL_UNLOCK(hcryp);
6995#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6996 /*Call registered error callback*/
6997 hcryp->ErrorCallback(hcryp);
6998#else
6999 /*Call legacy weak error callback*/
7000 HAL_CRYP_ErrorCallback(hcryp);
7001#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
7002 }
7003 /* Clear CCF Flag */
7004 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
7005
7006 for (index = 0U; index < 4U; index++)
7007 {
7008 intermediate_data[index] = hcryp->Instance->DOUTR;
7009 }
7010 }/*End of Workaround 2*/
7011#endif /* End AES or CRYP */
7012}
7013#endif /* AES or GCM CCM defined*/
7014#if defined (CRYP)
7015#if defined (CRYP_CR_ALGOMODE_AES_GCM)
7023static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7024{
7025 uint32_t tickstart;
7026
7027 /* Get timeout */
7028 tickstart = HAL_GetTick();
7029
7030 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
7031 {
7032 /* Check for the Timeout */
7033 if (Timeout != HAL_MAX_DELAY)
7034 {
7035 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7036 {
7037 return HAL_ERROR;
7038 }
7039 }
7040 }
7041 return HAL_OK;
7042}
7043#endif /* GCM CCM defined*/
7051static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7052{
7053 uint32_t tickstart;
7054
7055 /* Get timeout */
7056 tickstart = HAL_GetTick();
7057
7058 while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
7059 {
7060 /* Check for the Timeout */
7061 if (Timeout != HAL_MAX_DELAY)
7062 {
7063 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7064 {
7065 return HAL_ERROR;
7066 }
7067 }
7068 }
7069 return HAL_OK;
7070}
7071
7072
7080static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7081{
7082 uint32_t tickstart;
7083
7084 /* Get timeout */
7085 tickstart = HAL_GetTick();
7086
7087 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
7088 {
7089 /* Check for the Timeout */
7090 if (Timeout != HAL_MAX_DELAY)
7091 {
7092 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7093 {
7094 return HAL_ERROR;
7095 }
7096 }
7097 }
7098 return HAL_OK;
7099}
7100
7101#else /* AES */
7102
7110static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7111{
7112 uint32_t tickstart;
7113
7114 /* Get timeout */
7115 tickstart = HAL_GetTick();
7116
7117 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
7118 {
7119 /* Check for the Timeout */
7120 if (Timeout != HAL_MAX_DELAY)
7121 {
7122 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7123 {
7124 return HAL_ERROR;
7125 }
7126 }
7127 }
7128 return HAL_OK;
7129}
7130
7131#endif /* End AES or CRYP */
7132
7133
7148#endif /* HAL_CRYP_MODULE_ENABLED */
7149
7150
7154#endif /* TinyAES or CRYP*/
CRYP_AES_ECB
#define CRYP_AES_ECB
Definition stm32f4xx_hal_cryp.h:245
CRYP_AES_CBC
#define CRYP_AES_CBC
Definition stm32f4xx_hal_cryp.h:246
CRYP_AES_GCM_GMAC
#define CRYP_AES_GCM_GMAC
Definition stm32f4xx_hal_cryp.h:248
CRYP_AES_CCM
#define CRYP_AES_CCM
Definition stm32f4xx_hal_cryp.h:249
CRYP_AES_CTR
#define CRYP_AES_CTR
Definition stm32f4xx_hal_cryp.h:247
CRYP_KEYIVCONFIG_ONCE
#define CRYP_KEYIVCONFIG_ONCE
Definition stm32f4xx_hal_cryp.h:342
CRYP_DATATYPE_8B
#define CRYP_DATATYPE_8B
Definition stm32f4xx_hal_cryp.h:282
CRYP_DATATYPE_1B
#define CRYP_DATATYPE_1B
Definition stm32f4xx_hal_cryp.h:283
CRYP_DATATYPE_16B
#define CRYP_DATATYPE_16B
Definition stm32f4xx_hal_cryp.h:281
CRYP_DATATYPE_32B
#define CRYP_DATATYPE_32B
Definition stm32f4xx_hal_cryp.h:280
CRYP_DATAWIDTHUNIT_WORD
#define CRYP_DATAWIDTHUNIT_WORD
Definition stm32f4xx_hal_cryp.h:210
HAL_CRYP_ERROR_DMA
#define HAL_CRYP_ERROR_DMA
Definition stm32f4xx_hal_cryp.h:194
HAL_CRYP_ERROR_NOT_SUPPORTED
#define HAL_CRYP_ERROR_NOT_SUPPORTED
Definition stm32f4xx_hal_cryp.h:197
HAL_CRYP_ERROR_NONE
#define HAL_CRYP_ERROR_NONE
Definition stm32f4xx_hal_cryp.h:191
HAL_CRYP_ERROR_BUSY
#define HAL_CRYP_ERROR_BUSY
Definition stm32f4xx_hal_cryp.h:195
HAL_CRYP_ERROR_TIMEOUT
#define HAL_CRYP_ERROR_TIMEOUT
Definition stm32f4xx_hal_cryp.h:196
HAL_CRYP_ERROR_READ
#define HAL_CRYP_ERROR_READ
Definition stm32f4xx_hal_cryp.h:193
HAL_CRYP_ERROR_WRITE
#define HAL_CRYP_ERROR_WRITE
Definition stm32f4xx_hal_cryp.h:192
HAL_CRYP_MspDeInit
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
DeInitializes CRYP MSP.
Definition stm32f4xx_hal_cryp.c:710
HAL_CRYP_MspInit
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
Initializes the CRYP MSP.
Definition stm32f4xx_hal_cryp.c:694
HAL_CRYP_GetConfig
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Get CRYP Configuration parameters in associated handle.
Definition stm32f4xx_hal_cryp.c:640
HAL_CRYP_DeInit
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
De-Initializes the CRYP peripheral.
Definition stm32f4xx_hal_cryp.c:505
HAL_CRYP_SetConfig
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
Configure the CRYP according to the specified parameters in the CRYP_ConfigTypeDef.
Definition stm32f4xx_hal_cryp.c:558
HAL_CRYP_Init
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
Initializes the CRYP according to the specified parameters in the CRYP_ConfigTypeDef and creates the ...
Definition stm32f4xx_hal_cryp.c:430
HAL_CRYP_Encrypt_IT
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in interrupt mode.
Definition stm32f4xx_hal_cryp.c:1292
HAL_CRYP_Decrypt_IT
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in itnterrupt mode.
Definition stm32f4xx_hal_cryp.c:1455
HAL_CRYP_Decrypt_DMA
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Decryption in DMA mode.
Definition stm32f4xx_hal_cryp.c:1854
HAL_CRYP_Encrypt
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Encryption mode.
Definition stm32f4xx_hal_cryp.c:946
HAL_CRYP_Decrypt
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
Decryption mode.
Definition stm32f4xx_hal_cryp.c:1119
HAL_CRYP_Encrypt_DMA
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
Encryption in DMA mode.
Definition stm32f4xx_hal_cryp.c:1622
HAL_CRYP_GetError
uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
Return the CRYP error code.
Definition stm32f4xx_hal_cryp.c:2137
HAL_CRYP_InCpltCallback
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
Input FIFO transfer completed callback.
Definition stm32f4xx_hal_cryp.c:2159
HAL_CRYP_IRQHandler
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
This function handles cryptographic interrupt request.
Definition stm32f4xx_hal_cryp.c:2035
HAL_CRYP_ErrorCallback
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
CRYP error callback.
Definition stm32f4xx_hal_cryp.c:2191
HAL_CRYP_GetState
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
Returns the CRYP state.
Definition stm32f4xx_hal_cryp.c:2148
HAL_CRYP_OutCpltCallback
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
Output FIFO transfer completed callback.
Definition stm32f4xx_hal_cryp.c:2175
__HAL_CRYP_CLEAR_FLAG
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the CRYP pending status flag.
Definition stm32f4xx_hal_cryp.h:421
__HAL_CRYP_ENABLE_IT
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the CRYP interrupt.
Definition stm32f4xx_hal_cryp.h:472
__HAL_CRYP_GET_IT_SOURCE
#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
Check whether the specified CRYP interrupt source is enabled or not.
Definition stm32f4xx_hal_cryp.h:433
__HAL_CRYP_DISABLE
#define __HAL_CRYP_DISABLE(__HANDLE__)
Definition stm32f4xx_hal_cryp.h:382
__HAL_CRYP_GET_IT
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__)
Check whether the specified CRYP interrupt is set or not.
Definition stm32f4xx_hal_cryp.h:454
__HAL_CRYP_DISABLE_IT
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the CRYP interrupt.
Definition stm32f4xx_hal_cryp.h:490
__HAL_CRYP_ENABLE
#define __HAL_CRYP_ENABLE(__HANDLE__)
Enable/Disable the CRYP peripheral.
Definition stm32f4xx_hal_cryp.h:381
__HAL_CRYP_GET_FLAG
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__)
Definition stm32f4xx_hal_cryp.h:408
HAL_CRYP_STATETypeDef
HAL_CRYP_STATETypeDef
CRYP State Structure definition.
Definition stm32f4xx_hal_cryp.h:80
HAL_CRYP_STATE_READY
@ HAL_CRYP_STATE_READY
Definition stm32f4xx_hal_cryp.h:82
HAL_CRYP_STATE_RESET
@ HAL_CRYP_STATE_RESET
Definition stm32f4xx_hal_cryp.h:81
HAL_CRYP_STATE_BUSY
@ HAL_CRYP_STATE_BUSY
Definition stm32f4xx_hal_cryp.h:83
CRYP_FLAG_BUSY
#define CRYP_FLAG_BUSY
Definition stm32f4xx_hal_cryp.h:324
CRYP_ERR_CLEAR
#define CRYP_ERR_CLEAR
Definition stm32f4xx_hal_cryp.h:330
CRYP_CCF_CLEAR
#define CRYP_CCF_CLEAR
Definition stm32f4xx_hal_cryp.h:329
CRYP_HEADERWIDTHUNIT_WORD
#define CRYP_HEADERWIDTHUNIT_WORD
Definition stm32f4xx_hal_cryp.h:221
IS_CRYP_KEYSIZE
#define IS_CRYP_KEYSIZE(KEYSIZE)
Definition stm32f4xx_hal_cryp.h:600
IS_CRYP_INIT
#define IS_CRYP_INIT(CONFIG)
Definition stm32f4xx_hal_cryp.h:609
IS_CRYP_DATATYPE
#define IS_CRYP_DATATYPE(DATATYPE)
Definition stm32f4xx_hal_cryp.h:604
IS_CRYP_ALGORITHM
#define IS_CRYP_ALGORITHM(ALGORITHM)
Definition stm32f4xx_hal_cryp.h:593
CRYP_IT_RDERR
#define CRYP_IT_RDERR
Definition stm32f4xx_hal_cryp.h:300
CRYP_IT_CCF
#define CRYP_IT_CCF
Definition stm32f4xx_hal_cryp.h:301
CRYP_IT_CCFIE
#define CRYP_IT_CCFIE
Definition stm32f4xx_hal_cryp.h:297
CRYP_IT_WRERR
#define CRYP_IT_WRERR
Definition stm32f4xx_hal_cryp.h:299
CRYP_IT_ERRIE
#define CRYP_IT_ERRIE
Definition stm32f4xx_hal_cryp.h:298
CRYP_KEYSIZE_128B
#define CRYP_KEYSIZE_128B
Definition stm32f4xx_hal_cryp.h:264
CRYP_KEYSIZE_256B
#define CRYP_KEYSIZE_256B
Definition stm32f4xx_hal_cryp.h:265
CRYP_OPERATINGMODE_ENCRYPT
#define CRYP_OPERATINGMODE_ENCRYPT
Definition stm32f4xx_hal_cryp.c:287
CRYP_PHASE_HEADER
#define CRYP_PHASE_HEADER
Definition stm32f4xx_hal_cryp.c:292
CRYP_CCM_CTR1_0
#define CRYP_CCM_CTR1_0
Definition stm32f4xx_hal_cryp.c:305
CRYP_OPERATINGMODE_KEYDERIVATION
#define CRYP_OPERATINGMODE_KEYDERIVATION
Definition stm32f4xx_hal_cryp.c:288
CRYP_OPERATINGMODE_DECRYPT
#define CRYP_OPERATINGMODE_DECRYPT
Definition stm32f4xx_hal_cryp.c:289
CRYP_PHASE_PROCESS
#define CRYP_PHASE_PROCESS
Definition stm32f4xx_hal_cryp.c:284
CRYP_PHASE_INIT
#define CRYP_PHASE_INIT
Definition stm32f4xx_hal_cryp.c:291
CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT
#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT
Definition stm32f4xx_hal_cryp.c:290
CRYP_TIMEOUT_GCMCCMINITPHASE
#define CRYP_TIMEOUT_GCMCCMINITPHASE
Definition stm32f4xx_hal_cryp.c:280
CRYP_TIMEOUT_GCMCCMHEADERPHASE
#define CRYP_TIMEOUT_GCMCCMHEADERPHASE
Definition stm32f4xx_hal_cryp.c:281
CRYP_CCM_CTR1_2
#define CRYP_CCM_CTR1_2
Definition stm32f4xx_hal_cryp.c:307
CRYP_PHASE_PAYLOAD
#define CRYP_PHASE_PAYLOAD
Definition stm32f4xx_hal_cryp.c:293
CRYP_CCM_CTR1_1
#define CRYP_CCM_CTR1_1
Definition stm32f4xx_hal_cryp.c:306
CRYP_PHASE_FINAL
#define CRYP_PHASE_FINAL
Definition stm32f4xx_hal_cryp.c:294
CRYP_PHASE_READY
#define CRYP_PHASE_READY
Definition stm32f4xx_hal_cryp.c:283
CRYP_TIMEOUT_KEYPREPARATION
#define CRYP_TIMEOUT_KEYPREPARATION
Definition stm32f4xx_hal_cryp.c:279
CRYP_AES_IT
static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
Handle CRYP block input/output data handling under interruption.
Definition stm32f4xx_hal_cryp.c:3445
CRYP_AES_ProcessData
static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout)
Process Data: Write Input data in polling mode and used in AES functions.
Definition stm32f4xx_hal_cryp.c:3318
CRYP_AESGCM_Process_DMA
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA.
Definition stm32f4xx_hal_cryp.c:4162
CRYP_SetKey
static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
Writes Key in Key registers.
Definition stm32f4xx_hal_cryp.c:3614
CRYP_WaitOnCCFlag
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
Definition stm32f4xx_hal_cryp.c:7110
CRYP_GCMCCM_SetHeaderPhase
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Sets the header phase in polling mode.
Definition stm32f4xx_hal_cryp.c:5622
CRYP_AES_Decrypt
static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Decryption in ECB/CBC & CTR mode with AES Standard.
Definition stm32f4xx_hal_cryp.c:2577
CRYP_DMAError
static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
DMA CRYP communication error callback.
Definition stm32f4xx_hal_cryp.c:3169
CRYP_AES_Encrypt_IT
static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
Definition stm32f4xx_hal_cryp.c:2479
CRYP_AESCCM_Process
static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
AES CCM encryption/decryption processing in polling mode for TinyAES IP, no encrypt/decrypt performed...
Definition stm32f4xx_hal_cryp.c:4342
CRYP_SetDMAConfig
static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
Set the DMA configuration and start the DMA transfer.
Definition stm32f4xx_hal_cryp.c:3205
CRYP_Workaround
static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Workaround used for GCM/CCM mode.
Definition stm32f4xx_hal_cryp.c:6511
CRYP_AESCCM_Process_DMA
static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in DMA mode for TinyAES IP, no encrypt/decrypt performed,...
Definition stm32f4xx_hal_cryp.c:4926
CRYP_GCMCCM_SetPayloadPhase_IT
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
Sets the payload phase in interrupt mode.
Definition stm32f4xx_hal_cryp.c:5347
CRYP_AESCCM_Process_IT
static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
AES CCM encryption/decryption process in interrupt mode for TinyAES IP, no encrypt/decrypt performed,...
Definition stm32f4xx_hal_cryp.c:4769
CRYP_GCMCCM_SetHeaderPhase_DMA
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
Sets the header phase when using DMA in process.
Definition stm32f4xx_hal_cryp.c:5925
CRYP_GCMCCM_SetHeaderPhase_IT
static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
Sets the header phase in interrupt mode.
Definition stm32f4xx_hal_cryp.c:6273
CRYP_AES_Encrypt
static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption in ECB/CBC & CTR Algorithm with AES Standard.
Definition stm32f4xx_hal_cryp.c:2401
CRYP_AESGCM_Process
static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG.
Definition stm32f4xx_hal_cryp.c:3682
CRYP_AES_Decrypt_IT
static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode.
Definition stm32f4xx_hal_cryp.c:2728
CRYP_DMAOutCplt
static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
DMA CRYP output data process complete callback.
Definition stm32f4xx_hal_cryp.c:3114
CRYP_DMAInCplt
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
DMA CRYP input data process complete callback.
Definition stm32f4xx_hal_cryp.c:3073
CRYP_AES_Decrypt_DMA
static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode.
Definition stm32f4xx_hal_cryp.c:2914
CRYP_AESGCM_Process_IT
static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode.
Definition stm32f4xx_hal_cryp.c:3880
CRYP_SET_PHASE
#define CRYP_SET_PHASE(__HANDLE__, __PHASE__)
Definition stm32f4xx_hal_cryp.c:329
HAL_DMA_Start_IT
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
Definition stm32f4xx_hal_dma.c:451
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition stm32f4xx_hal.c:323
assert_param
#define assert_param(expr)
Definition stm32_assert_template.h:46
stm32f4xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
HAL_IS_BIT_SET
#define HAL_IS_BIT_SET(REG, BIT)
Definition stm32f4xx_hal_def.h:63
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition stm32f4xx_hal_def.h:39
HAL_ERROR
@ HAL_ERROR
Definition stm32f4xx_hal_def.h:41
HAL_OK
@ HAL_OK
Definition stm32f4xx_hal_def.h:40
UNUSED
#define UNUSED(X)
Definition stm32f4xx_hal_def.h:58
__HAL_UNLOCK
#define __HAL_UNLOCK(__HANDLE__)
Definition stm32f4xx_hal_def.h:105
HAL_IS_BIT_CLR
#define HAL_IS_BIT_CLR(REG, BIT)
Definition stm32f4xx_hal_def.h:64
HAL_MAX_DELAY
#define HAL_MAX_DELAY
Definition stm32f4xx_hal_def.h:61
HAL_UNLOCKED
@ HAL_UNLOCKED
Definition stm32f4xx_hal_def.h:51
__HAL_LOCK
#define __HAL_LOCK(__HANDLE__)
Definition stm32f4xx_hal_def.h:93
CRYP_ConfigTypeDef
CRYP Init Structure definition.
Definition stm32f4xx_hal_cryp.h:50
CRYP_ConfigTypeDef::KeyIVConfigSkip
uint32_t KeyIVConfigSkip
Definition stm32f4xx_hal_cryp.h:68
CRYP_ConfigTypeDef::pKey
uint32_t * pKey
Definition stm32f4xx_hal_cryp.h:55
CRYP_ConfigTypeDef::DataWidthUnit
uint32_t DataWidthUnit
Definition stm32f4xx_hal_cryp.h:66
CRYP_ConfigTypeDef::HeaderSize
uint32_t HeaderSize
Definition stm32f4xx_hal_cryp.h:64
CRYP_ConfigTypeDef::KeySize
uint32_t KeySize
Definition stm32f4xx_hal_cryp.h:53
CRYP_ConfigTypeDef::B0
uint32_t * B0
Definition stm32f4xx_hal_cryp.h:65
CRYP_ConfigTypeDef::Algorithm
uint32_t Algorithm
Definition stm32f4xx_hal_cryp.h:58
CRYP_ConfigTypeDef::DataType
uint32_t DataType
Definition stm32f4xx_hal_cryp.h:51
CRYP_ConfigTypeDef::HeaderWidthUnit
uint32_t HeaderWidthUnit
Definition stm32f4xx_hal_cryp.h:67
CRYP_ConfigTypeDef::pInitVect
uint32_t * pInitVect
Definition stm32f4xx_hal_cryp.h:56
CRYP_ConfigTypeDef::Header
uint32_t * Header
Definition stm32f4xx_hal_cryp.h:61
__CRYP_HandleTypeDef
CRYP handle Structure definition.
Definition stm32f4xx_hal_cryp.h:92
__CRYP_HandleTypeDef::State
__IO HAL_CRYP_STATETypeDef State
Definition stm32f4xx_hal_cryp.h:124
__CRYP_HandleTypeDef::KeyIVConfig
uint32_t KeyIVConfig
Definition stm32f4xx_hal_cryp.h:128
__CRYP_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition stm32f4xx_hal_cryp.h:122
__CRYP_HandleTypeDef::SizesSum
uint32_t SizesSum
Definition stm32f4xx_hal_cryp.h:131
__CRYP_HandleTypeDef::Init
CRYP_ConfigTypeDef Init
Definition stm32f4xx_hal_cryp.h:99
__CRYP_HandleTypeDef::Size
uint16_t Size
Definition stm32f4xx_hal_cryp.h:114
__CRYP_HandleTypeDef::Instance
AES_TypeDef * Instance
Definition stm32f4xx_hal_cryp.h:96
__CRYP_HandleTypeDef::AutoKeyDerivation
FunctionalState AutoKeyDerivation
Definition stm32f4xx_hal_cryp.h:101
__CRYP_HandleTypeDef::Phase
uint32_t Phase
Definition stm32f4xx_hal_cryp.h:116
__CRYP_HandleTypeDef::CrypHeaderCount
__IO uint16_t CrypHeaderCount
Definition stm32f4xx_hal_cryp.h:108
__CRYP_HandleTypeDef::hdmaout
DMA_HandleTypeDef * hdmaout
Definition stm32f4xx_hal_cryp.h:120
__CRYP_HandleTypeDef::pCrypOutBuffPtr
uint32_t * pCrypOutBuffPtr
Definition stm32f4xx_hal_cryp.h:106
__CRYP_HandleTypeDef::CrypOutCount
__IO uint16_t CrypOutCount
Definition stm32f4xx_hal_cryp.h:112
__CRYP_HandleTypeDef::pCrypInBuffPtr
uint32_t * pCrypInBuffPtr
Definition stm32f4xx_hal_cryp.h:104
__CRYP_HandleTypeDef::CrypInCount
__IO uint16_t CrypInCount
Definition stm32f4xx_hal_cryp.h:110
__CRYP_HandleTypeDef::hdmain
DMA_HandleTypeDef * hdmain
Definition stm32f4xx_hal_cryp.h:118
__CRYP_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition stm32f4xx_hal_cryp.h:126
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition stm32f4xx_hal_dma.h:139
__DMA_HandleTypeDef::XferCpltCallback
void(* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition stm32f4xx_hal_dma.h:150
__DMA_HandleTypeDef::XferErrorCallback
void(* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)
Definition stm32f4xx_hal_dma.h:158